DAQ Meeting/20180728

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  • Bob : Teach Cameron and Chandan how to test HAPPEX ADC channels and look at data read into CODA


Morning - 9AM - Bob, Cameron, Chandan

  • Plan to test ADCs
    • Calibrate 12 (maximum value = 4095) and 16 bit (maximum value = 65535) Digital to Analog Converters (DACs) - find the range and the values of the outputs for given software inputs on the HAPPEX timing boards
    • Learn to adjust the conversion (conv) and integrator (int) gains on the HAPPEX 18 bit ADCs
      • The total gain is a combination of the two gains and we want to optimize so that a 5V input signal to the ADC reaches around 75% of the dynamic range (so that no large pulse will hit the saturation point, but that the signal's precision isn't lost to the low bit resolution)
      • Do this initially for 30Hz helicity flip rate
      • 240Hz flip rate will integrate for less time, so it may be necessary to turn up the gains so that the bit resolution doesn't become a factor (the pedestal value may move with changing helicity flip rate)
  • Big Green Monster
    • ROOT GUI (written by Kent) that allows you to set gains, etc. for experiment running online
    • apar@adaq3:~/vxworks/*.boot scripts set HAPTB settings at boot (should be set for the ideal settings observed during testing)
    • These HAPTB gain settings are also settable in .crl files run by CODA during data-taking
  • To test the HAPTB DAC settings we can also execute commands in the vxworks computer itself by logging in via telnet
    • Command: setTimeHAPTB(startTime,lengthOfRamp) - where startTime + lengthOfRamp should be = 1/frequencyOfQuartets from the injector
    • Command: setDACHAPTB(DAC#,value) - where the DAC number is 1 for the 12 bit DAC and 2 is the 16 bit DAC output, and value is a number from 1 to the upper limit (4095 and 65535 respectively)
    • There is a rampdac12 user string (defined in usrstrutils.c) that can be added to the user strings of the CODA configuration to turn it on
      • This will automatically ramp the DAC from MIN_DAC12 to MAX_DAC12 if rampdac12==1 (which it does when the user string is added)
      • The getflag() command reads the config string in the .crl
      • We will add a rampdac16 equivalent ramp function and user string
      • usrstrutils.C can be modified to allow new functions (rampdac16 will be added and made into RampTest.crl)
  • To set the HAPTB gains we should use these commands
    • Command: adc18_setconv(ADC#,gainValue) - where the ADC# is the index from left to right of the ADC to set the gain in the HAPPEX crate, gainValue is the value of the conv gain from 0 to 15 where 0 is low
    • Command: adc18_intgain(ADC#,gainValue) - where ADC# is the same, and gainValue runs from 0 to 3, where 3 is the minimum now
    • The commands are from .o files loaded at boot with the .boot script
    • The philosophy of setting the gains at boot is from Caryn:
      • Set the gains in vxworks boot scripts
      • Allow the Green Monster to edit the gains too
      • Read gains in .crl and store/reset those values during runs
    • Currently we are hardcode setting the gains in Prex_ts.crl (in ~/devices/crl - added to HallA-Parity-DAQ repository)
      • Compile with makelist Prex_ts.crl ppc
      • int gain = 3 (minimum)
      • conv gain = 1 (very low)
      • We turn on ramping in the user config strings in the run-database to test the ADCs
      • but we should also check the physical resistors themselves to make sure things are behaving how they should
      • It would be nice to get a live readout system running in PAN or JAPAN so that testing ADCs can be done online
      • The HAPPEX 18 bit ADCs signal is digitized and 2^18 maxes out at 262,144 (so we need to set the 5 volt signal to reside at round 75% of that value for dynamic range safety)
  • Metrics of a good ADC channel
    • It turns on, works, and responds to signal
    • Sees a 5 volt signal at ~75% of saturation for 30Hz helicity flip rate (vary and change the gains so this is the case)
    • Look at neighboring channel's pedestal pulses to see that they only vary within 4 or 5 ADC channels
    • Look to see if the inputted helicity signal shows up in long term pedestals at a 1ppb maximum level (crosstalk study)
    • See about switching helicity flip rates and checking the timing of the HAPTB on a scope
    • Ensure that pedestals stay still, slopes are straight, and neighboring ADC channels don't interfere with eachother
    • Make sure that the "base" pedestal level isn't saturating and railing at the low end
    • Make sure there is some lee-way with several gain options on the low end to choose from (so we aren't stuck with just the lowest gain setting or something)
    • Control.db in bpan18/pan/control.db needs to have the database exactly correct in order for the data analysis to make sense
      • This can be automatically generated by a perl script written by Bryan Moffit
  • We wrote a RampTest.crl rampdac12 and rampdac16 .crl file that has a flattening off at the 5V position so we can check that the 5V signal shows up at the 75% of dynamic range and we used it (see Today's testing)
  • We should compile and test spare modles, and make a toolbox with everything needed for testing them
  • We should improve setupxterms script that is used to open a bunch of xterm windows with the commands needed to log into the ROCs and DAQ computers


Today's testing