DAQ Testing/20180727

Main Page - DAQ Testing - July 27th, 2018 Testers: Cameron and Chandan

Goal: Test HAPPEX and QWeak ADCs in Right HRS Parity DAQ for functionality and dynamic range

Calibrate RHRS HAPPEX Timing Board (HAPTB ) 12 and 16 bit DAC

To calibrate the 12 and 16 bit DACs we:

• Log into the RHRS ROC with telnet (see Network Map)
• Set the DAC output level with the C code command setDACHAPTB(DAC#,Level#)
• Read the DAC output level with a voltmeter
  • DAC# 1 = 12bit, 2 = 16 bit
  • 12 Bit DAC Level# unknown scale, testing with voltmeter determines - expect positive voltages for values that range within Level ⊂ [0, 2^12 - 1 = 4095] modularly
    • Level = 200 -> Voltage read = 0.480V
    • Level = 300 -> Voltage read = 0.731V
    • Level = 400 -> Voltage read = 0.976V
    • Level = 500 -> Voltage read = 1.220V
    • Level = 600 -> Voltage read = 1.464V
    • Level = 700 -> Voltage read = 1.708V
    • Level = 800 -> Voltage read = 1.952V
    • Level = 900 -> Voltage read = 2.19V
    • Level = 1000 -> Voltage read = 2.44V
    • Level = 1100 -> Voltage read = 2.68V
    • Level = 1200 -> Voltage read = 2.92V
    • Level = 1300 -> Voltage read = 3.17V
    • Level = 1400 -> Voltage read = 3.41V
    • Level = 1500 -> Voltage read = 3.66V
    • Level = 1600 -> Voltage read = 3.90V
    • Level = 1700 -> Voltage read = 4.15V
    • Level = 1800 -> Voltage read = 4.39V
    • Level = 1900 -> Voltage read = 4.63V
    • Level = 2000 -> Voltage read = 4.88V
    • Level = 2100 -> Voltage read = 5.12V
    • Level = 3000 -> Voltage read = 7.32V
    • Functional V = 0.0024402 * Level - 0.00257905
  • 16 Bit DAC Level# unknown scale, testing with voltmeter determines - expect negative to positive voltages for values that range within Level ⊂ [0, 2^16 - 1 = 65535] modularly
    • Level = 300 -> Voltage read = -4.92V
    • Level = 400 -> Voltage read = -4.94V
    • Level = 500 -> Voltage read = -4.92V
    • Level = 2000 -> Voltage read = -4.69V
    • Level = 3000 -> Voltage read = -4.54V
    • Level = 8000 -> Voltage read = -3.77V
    • Level = 12000 -> Voltage read = -3.16V
    • Level = 16000 -> Voltage read = -2.55V
    • Level = 20000 -> Voltage read = -1.94V
    • Level = 24000 -> Voltage read = -1.32V
    • Level = 28000 -> Voltage read = -0.72V
    • Level = 32000 -> Voltage read = -0.07V
    • Level = 36000 -> Voltage read = 0.49V
    • Level = 40000 -> Voltage read = 1.10V
    • Level = 44000 -> Voltage read = 1.71V
    • Level = 48000 -> Voltage read = 2.32V
    • Level = 52000 -> Voltage read = 2.93V
    • Level = 56000 -> Voltage read = 3.54V
    • Level = 60000 -> Voltage read = 4.15V
    • Level = 64000 -> Voltage read = 4.76V
    • Level = 68000 -> Voltage read = -4.61V (Modular wraps around)
    • Functional V = 0.000152329 * Level - 4.9871

Testing LHRS HAPPEX ADCs using 12bit DAC

• To test an ADC channel
  • Set a specific ADC slot and channel number's gains in the Prex_ts.crl file (in ~/devices/crl/) and make with "makelist Prex_ts.crl ppc"
  • Run through several DAC values and ensure that the base and peak values (adcx#_#_b0 or p0) are not railed to minimum or maximum values
  • Reset the conversion and integrator gain values with functions
    • adc18_intgain(adcModule#,value#) - min = 3, max = 0
    • adc18_setconv(adcModule#,value#) - min = 0, max = 15
    • in Prex_ts.crl around lines 543 and 544 - inside a loop that sets every single ADC channel and gain in all DAQs
    • Set to lower net level first, and scan up
    • to see how high a gain can still read the peak 5V voltage from DAC at ~75% of saturation level
  • We are testing with 30Hz helicity flip rate (longest integration time, most likely to saturate, probably will be used for CREX)
  • Metrics - analyze a run's output with ~/adc18_ana/newrun run# numEvents# roc# slot#
• RHRS "adcx2" according to tape = first ADC on the left (of two options) of the 18bit ADC crate; address = 0 in ROC26 crate, name = adcx7 in ~/bpan18/pan/control.db
  • test by logging into HAPPEX7 via telnet and running int and conv gain setting in there while CODA takes data in the background
  • First channel test - 12 bit DAC
    • Run number 4040 - Level = (300, 500, 700, 1400, 2000, 3000, 500)
      • "adc18_ana/newrun 4040 5500 26 0" yields an output file ~/adc18_ana/adc18_4040.root with NTuple adc18 inside
      • Plotting with "adc18->Draw("adc0:event") we see signals, but miss the last 500 Level region, and it doesn't look like it saturates (even thought the voltage into the channel is 7.3 volts, higher than the quoted 5 volts)
    • Run number 4041 - set the level to 500 (~1.22 Volts 12 bit DAC) flat the whole time for 2600 events
      • Plotting adc0:event shows that the level comes out to ~28000, which is ~12% of the supposed range of the 18 bit ADCs
    • Run number 4042 - 500, 800, 1000, 1400, 400, 1800, 2000, 2400, 400
      • Plotting adc0:event shows again that we don't saturate - the peak value is just 140,000 now (for 2400 Level ~ 6 volts input signal)