DAQ Testing/20180727

Main Page - DAQ Testing - July 27th, 2018 Testers: Cameron and Chandan

Goal: Test HAPPEX and QWeak ADCs in Right HRS Parity DAQ for functionality and dynamic range

Calibrate RHRS HAPPEX Timing Board (HAPTB ) 12 and 16 bit DAC

To calibrate the 12 and 16 bit DACs we:

• Log into the RHRS ROC with telnet (see Network Map)
• Set the DAC output level with the C code command setDACHAPTB(DAC#,Level#)
• Read the DAC output level with a voltmeter
  • DAC# 1 = 12bit, 2 = 16 bit
  • 12 Bit DAC Level# unknown scale, testing with voltmeter determines - expect positive voltages for values that range within Level ⊂ [0, 2^12 - 1 = 4095] modularly
    • Level = 200 -> Voltage read = 0.480V
    • Level = 300 -> Voltage read = 0.731V
    • Level = 400 -> Voltage read = 0.976V
    • Level = 500 -> Voltage read = 1.220V
    • Level = 600 -> Voltage read = 1.464V
    • Level = 700 -> Voltage read = 1.708V
    • Level = 800 -> Voltage read = 1.952V
    • Level = 900 -> Voltage read = 2.19V
    • Level = 1000 -> Voltage read = 2.44V
    • Level = 1100 -> Voltage read = 2.68V
    • Level = 1200 -> Voltage read = 2.92V
    • Level = 1300 -> Voltage read = 3.17V
    • Level = 1400 -> Voltage read = 3.41V
    • Level = 1500 -> Voltage read = 3.66V
    • Level = 1600 -> Voltage read = 3.90V
    • Level = 1700 -> Voltage read = 4.15V
    • Level = 1800 -> Voltage read = 4.39V
    • Level = 1900 -> Voltage read = 4.63V
    • Level = 2000 -> Voltage read = 4.88V
    • Level = 2100 -> Voltage read = 5.12V
    • Level = 3000 -> Voltage read = 7.32V
    • Functional V = 0.0024402 * Level - 0.00257905
  • 16 Bit DAC Level# unknown scale, testing with voltmeter determines - expect negative to positive voltages for values that range within Level ⊂ [0, 2^16 - 1 = 65535] modularly
    • Level = 300 -> Voltage read = -4.92V
    • Level = 400 -> Voltage read = -4.94V
    • Level = 500 -> Voltage read = -4.92V
    • Level = 2000 -> Voltage read = -4.69V
    • Level = 3000 -> Voltage read = -4.54V
    • Level = 8000 -> Voltage read = -3.77V
    • Level = 12000 -> Voltage read = -3.16V
    • Level = 16000 -> Voltage read = -2.55V
    • Level = 20000 -> Voltage read = -1.94V
    • Level = 24000 -> Voltage read = -1.32V
    • Level = 28000 -> Voltage read = -0.72V
    • Level = 32000 -> Voltage read = -0.07V
    • Level = 36000 -> Voltage read = 0.49V
    • Level = 40000 -> Voltage read = 1.10V
    • Level = 44000 -> Voltage read = 1.71V
    • Level = 48000 -> Voltage read = 2.32V
    • Level = 52000 -> Voltage read = 2.93V
    • Level = 56000 -> Voltage read = 3.54V
    • Level = 60000 -> Voltage read = 4.15V
    • Level = 64000 -> Voltage read = 4.76V
    • Level = 68000 -> Voltage read = -4.61V (Modular wraps around)
    • Functional V = 0.000152329 * Level - 4.9871

Testing LHRS HAPPEX ADCs using 12bit DAC

• To test an ADC channel
  • Set a specific ADC slot and channel number's gains in the Prex_ts.crl file (in ~/devices/crl/) and make with "makelist Prex_ts.crl ppc"
  • Run through several DAC values and ensure that the base and peak values (adcx#_#_b0 or p0) are not railed to minimum or maximum values
  • Reset the conversion and integrator gain values with functions
    • adc18_intgain(adcModule#,value#) - min = 3, max = 0
    • adc18_setconv(adcModule#,value#) - min = 0, max = 15
    • in Prex_ts.crl around lines 543 and 544 - inside a loop that sets every single ADC channel and gain in all DAQs
    • Set to lower net level first, and scan up
    • to see how high a gain can still read the peak 5V voltage from DAC at ~75% of saturation level
  • We are testing with 30Hz helicity flip rate (longest integration time, most likely to saturate, probably will be used for CREX)
  • Metrics - analyze a run's output with ~/adc18_ana/newrun run# numEvents# roc# slot#
• RHRS "adcx2" according to tape = first ADC on the left (of two options) of the 18bit ADC crate; address = 0 in ROC26 crate, name = adcx7 in ~/bpan18/pan/control.db
  • test by logging into HAPPEX7 via telnet and running int and conv gain settings (adcModule#=0) in there while CODA takes data in the background
  • First channel test - 12 bit DAC
    • Run number 4040 - Level = 300, 500, 700, 1400, 2000, 3000, 500; conv = 1, int = 3
      • "adc18_ana/newrun 4040 5500 26 0" yields an output file ~/adc18_ana/adc18_4040.root with NTuple adc18 inside
      • Plotting with "adc18->Draw("adc0:event") we see signals, but miss the last 500 Level region, and it doesn't look like it saturates (even thought the voltage into the channel is 7.3 volts, higher than the quoted 5 volts)
    • Run number 4041 - set the level to 500 (~1.22 Volts 12 bit DAC) flat the whole time for 2600 events; conv = 1, int = 3
      • Plotting adc0:event shows that the level comes out to ~28000, which is ~12% of the supposed range of the 18 bit ADCs
    • Run number 4042 - 500, 800, 1000, 1400, 400, 1800, 2000, 2400, 400; conv = 1, int = 3
      • Plotting adc0:event shows again that we don't saturate - the peak value is just 140,000 now (for 2400 Level ~ 6 volts input signal)
    • Run number 4043 - set the gain to int 3, conv 1 (I thought I set 6, but maybe missed), run DAC from 500, 800, 1200, 1600, 2000, 2400
      • Plotting adc0:event should saturate probably
      • It doesn't - I think the gain settings are getting overwritten by hitting start new run in CODA...
    • Run number 4044 - recompiling the Prex_ts.crl with higher gain (int = 1 and conv = 10) hard coded in to try to see saturation, run DAC from 2800, 500, 800, 1200, 1800, 2000, 2100, 3000, 500
      • Plotting adc0:event should definitely saturate now
      • In fact it does - it saturates for all values tried, including 500
    • We need to figure out how to get the gain values to update and not get overwritten by the .crl defaults (do the reading trick where it assumes the boot script had set it up first?)
    • Not obvious, lets just use the .crl hard coded numbers for now to get an initial result (and reboot CODA)
    • Run number 4045 showed that .crl overwrites telnet adc18_setconv(0,#) or adc18_intgain(0,#) every time when the settings are hard coded
    • Run number 4046 uses int = 3, conv = 5; DAC level starts at 500, 800, 1200, 1600, 2000, 500, 2400
      • This shows saturation at around level 1900 (ADC reads 258000 flat y value for 2000 and 2400 settings)
      • We should reduce the gain again to achieve the desired 5V = 2100 level at the 75% max saturation (0.75*258000 ~= 193000 for level 2100)
    • Run number 4047 had a CODA error
    • Run number 4048 uses int = 3, conv = 3; DAC level starts at 500, 800, 1200, 1600, 1900, 2100, 500, 2400, 500
      • We want to see Level 2100 reach ~ 193000 ADC value (5V DAC output signal should see 75% of saturation level)
      • Plotting adc0:event shows the 5V signal at 235000 - this is above the 75% window, but it works and we will assume this is a reasonable value for now (see plot for details)
  • We decide to use the "rampdac12" function in the Prex_ts.crl and database to allow more rapid dynamic range tests and setting multiple gains in a single run
    • The ramp goes from 0 to a large value - when that large value gets bigger than 2^12 it wraps back aronud to zero, as one expects
    • First channel test - Run 4049 tests ramp function with previously determined optimal gains (int = 3, conv = 3)
      • The ramp goes once per cycle (30Hz) in 4 unit increments from 500 to 8000 (according to DAC_MIN12 and DAC_MAX12 variables in Prex_ts.crl file defaults - probably need to change)
    • Run 4050 - changing the ramp step size to 16 and made it so one cycle of the Ramp fits into 500 events (set minimum to 500, maximum to 8500- want to be able to set the gains every 1000 events to get consistent plots of ramps vs gain settings
      • Works
    • Run 4051 - set the gain to lowest settings (int = 3, conv = 0) to see that it still saturates around the Level 4000 mark probably
      • Doesn't saturate - converts Level 4000 ~ 10 Volts into 115000 ADC channel (half way to saturation only)
    • Run 4052 - set the gain to one we know was already mostly saturated, for Level 500 and higher (int = 2, conv = 10) - should all be saturated, except for when it loops back to zero
      • It saturates for ~600 and above, as expected
    • Run 4053 skipped
    • Run 4054 - set the gain to one value initially, then wait for 2 cycles ~ during 1000-1500 events change the gain to another value (proof of concept that changing gains mid run is possible) and end run at 2500 events
      • Works
    • Run 4055 - start with maxed maxed (int = 2, conv = 10), next go to medium high (int = 2, conv = 3), go to optimal-previously-decided-medium (int = 3, conv = 3), finish with low (int = 3, conv = 0)
      • Works, see plot
      • We want to have the one where the stripes have the half-way point (Level ~ 2100, Voltage ~ 5V) resting at 193000 ADC channel (75% of saturation level)
      • Add in a flat bit at the 2100 ~ 5V level for clarity
    • Run 4056 - repeat 4055 but with extra flat lines at 2100 Level ~ 5V for clarity
      • Error - forgot to reset number of steps counter to 0 after first pass - run again
    • Run 4057 - repeat, correct logic mistake
      • starts with int = 2, conv = 10
      • adc18_setconv(0,3) - medium high
      • adc18_intgain(0,3) - just right (int = 3, conv = 3) (actually 20% too high for my taste)
      • adc18_setconv(0,0) - too low
      • Result - It works (see plot)
    • Run 4058 - repeat, use just initial high values and int = 3, conv = 2 for perfect setting 5V at 75% of dynamic range
      • Result - it works - this is our chosen ADC 0 channel 0 ideal setting
  • Second channel test - 12 bit DAC