Difference between revisions of "DAQ Testing/20180727"

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Main Page - [[DAQ Testing]] - July 27th, 2018
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Back to [[Main_Page|Main Page]] >> [[DAQ_Doc_Portal|DAQ Documentation Portal]] >> [[DAQ_Testing|DAQ Testing]] >> [[DAQ_Commissioning_Notes|DAQ Commissioning Notes]]
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Testers: Cameron and Chandan
 
  
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Goal: Test HAPPEX and QWeak ADCs in Right HRS Parity DAQ for functionality and dynamic range
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>> [[DAQ_Testing/20180728|Next Day of Testing]]
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July 27th, 2018 Testers: Cameron and Chandan
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See [[DAQ_Meeting/20180727|Today's Meeting Notes]]
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== Goal ==
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Cameron and Chandan learn how to test DAC and ADCs with Bob Michaels
  
 
== Calibrate RHRS HAPPEX Timing Board (HAPTB ) 12 and 16 bit DAC ==
 
== Calibrate RHRS HAPPEX Timing Board (HAPTB ) 12 and 16 bit DAC ==
  
 
To calibrate the 12 and 16 bit DACs we:
 
To calibrate the 12 and 16 bit DACs we:
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* Log into the RHRS ROC with telnet (see [[DAQ_Networking|Network Map]])
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* Log into the RHRS ROC with telnet (see [[DAQ_Network_Map|Network Map]])
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* Set the DAC output level with the C code command setDACHAPTB(DAC#,Level#)
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* Set the DAC output level with the C code command '''setDACHAPTB(DAC#,Level#)'''
 
* Read the DAC output level with a voltmeter
 
* Read the DAC output level with a voltmeter
 
** DAC# 1 = 12bit, 2 = 16 bit
 
** DAC# 1 = 12bit, 2 = 16 bit
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** 12 Bit DAC Level# unknown scale, testing with voltmeter determines - expect positive voltages for values that range within Level ⊂ [0, 2^12 - 1 = 4095] modularly
 
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*** Level = 200 -> Voltage read = 0.480V
 
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*** Level = 300 -> Voltage read = 0.731V
 
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*** Level = 400 -> Voltage read = 0.976V
 
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*** Level = 500 -> Voltage read = 1.220V
 
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*** Level = 600 -> Voltage read = 1.464V
 
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*** Level = 700 -> Voltage read = 1.708V
 
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*** Level = 800 -> Voltage read = 1.952V
 
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*** Level = 900  -> Voltage read = 2.19V
 
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*** Level = 1000 -> Voltage read = 2.44V
 
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*** Level = 1100 -> Voltage read = 2.68V
 
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*** Level = 1200 -> Voltage read = 2.92V
 
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*** Level = 1300 -> Voltage read = 3.17V
 
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*** Level = 1400 -> Voltage read = 3.41V
 
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*** Level = 1500 -> Voltage read = 3.66V
 
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*** Level = 1600 -> Voltage read = 3.90V
 
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*** Level = 1700 -> Voltage read = 4.15V
 
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*** Level = 1800 -> Voltage read = 4.39V
 
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*** Level = 1900 -> Voltage read = 4.63V
 
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*** Level = 2000 -> Voltage read = 4.88V
 
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*** Level = 2100 -> Voltage read = 5.12V
 
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*** Level = 3000 -> Voltage read = 7.32V
 
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*** Functional V = 0.0024402 * Level - 0.00257905
 
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** 16 Bit DAC Level# unknown scale, testing with voltmeter determines - expect negative to positive voltages for values that range within Level ⊂ [0, 2^16 - 1 = 65535] modularly
 
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*** Level = 300 -> Voltage read = -4.92V
 
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*** Level = 400 -> Voltage read = -4.94V
 
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*** Level = 500 -> Voltage read = -4.92V
 
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*** Level = 2000 -> Voltage read = -4.69V
 
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*** Level = 3000 -> Voltage read = -4.54V
 
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*** Level = 8000 -> Voltage read = -3.77V
 
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*** Level = 12000 -> Voltage read = -3.16V
 
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*** Level = 16000 -> Voltage read = -2.55V
 
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*** Level = 20000 -> Voltage read = -1.94V
 
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*** Level = 24000 -> Voltage read = -1.32V
 
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*** Level = 28000 -> Voltage read = -0.72V
 
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*** Level = 32000 -> Voltage read = -0.07V
 
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*** Level = 36000 -> Voltage read = 0.49V
 
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*** Level = 40000 -> Voltage read = 1.10V
 
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*** Level = 44000 -> Voltage read = 1.71V
 
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*** Level = 48000 -> Voltage read = 2.32V
 
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*** Level = 52000 -> Voltage read = 2.93V
 
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*** Level = 56000 -> Voltage read = 3.54V
 
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*** Level = 60000 -> Voltage read = 4.15V
 
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*** Level = 64000 -> Voltage read = 4.76V
 
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*** Level = 68000 -> Voltage read = -4.61V (Modular wraps around)
 
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*** Functional V = 0.000152329 * Level - 4.9871
 
  
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== Testing LHRS HAPPEX ADCs using 12bit DAC ==
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== Testing RHRS HAPPEX ADCs using 12bit DAC ==
 
* To test an ADC channel
 
* To test an ADC channel
 
** Set a specific ADC slot and channel number's gains in the Prex_ts.crl file (in ~/devices/crl/) and make with "makelist Prex_ts.crl ppc"
 
** Set a specific ADC slot and channel number's gains in the Prex_ts.crl file (in ~/devices/crl/) and make with "makelist Prex_ts.crl ppc"
 
** Run through several DAC values and ensure that the base and peak values (adcx#_#_b0 or p0) are not railed to minimum or maximum values
 
** Run through several DAC values and ensure that the base and peak values (adcx#_#_b0 or p0) are not railed to minimum or maximum values
 
** Reset the conversion and integrator gain values with functions
 
** Reset the conversion and integrator gain values with functions
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*** adc18_intgain(adcModule#,value#) - min = 3, max = 0
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*** '''adc18_intgain(adcModule#,value#)''' - min = 3, max = 0
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*** adc18_setconv(adcModule#,value#) - min = 0, max = 15
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*** '''adc18_setconv(adcModule#,value#)''' - min = 0, max = 15
 
*** in Prex_ts.crl around lines 543 and 544 - inside a loop that sets every single ADC channel and gain in all DAQs
 
*** in Prex_ts.crl around lines 543 and 544 - inside a loop that sets every single ADC channel and gain in all DAQs
 
*** Set to lower net level first, and scan up
 
*** Set to lower net level first, and scan up
Line 70: Line 31:
 
** We are testing with 30Hz helicity flip rate (longest integration time, most likely to saturate, probably will be used for CREX)
 
** We are testing with 30Hz helicity flip rate (longest integration time, most likely to saturate, probably will be used for CREX)
 
** Metrics - analyze a run's output with ~/adc18_ana/newrun run# numEvents# roc# slot#
 
** Metrics - analyze a run's output with ~/adc18_ana/newrun run# numEvents# roc# slot#
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* RHRS "adcx2" according to tape = first ADC on the left (of two options) of the 18bit ADC crate; address = 0 in ROC26 crate, name = adcx7 in ~/bpan18/pan/control.db
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* RHRS "adcx2" according to tape label = first ADC on the left (of two options) of the 18bit ADC crate; address = 0 in ROC26 crate, name = adcx7 in ~/bpan18/pan/control.db
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** test by logging into HAPPEX7 via telnet and running int and conv gain setting in there while CODA takes data in the background
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** test by logging into HAPPEX7 via telnet and running int and conv gain settings (adcModule#=0) in there while CODA takes data in the background
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** First channel test - 12 bit DAC
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*** Run number 4040 - Level = (300, 500, 700, 1400, 2000, 3000, 500)
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== To Do ==
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**** "adc18_ana/newrun 4040 5500 26 0" yields an output file ~/adc18_ana/adc18_4040.root with NTuple adc18 inside
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* Test ADCs and continue in todo list
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**** Plotting with "adc18->Draw("adc0:event") we see signals, but miss the last 500 Level region, and it doesn't look like it saturates (even thought the voltage into the channel is 7.3 volts, higher than the quoted 5 volts)
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* Perfect and better justify parameters in Ramp testing function (and separate it out into a specific ramp-testing .crl file to avoid messing with the main Prex_ts.crl functionality)
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*** Run number 4041 - set the level to 500 (~1.22 Volts 12 bit DAC) flat the whole time for 2600 events
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* Move the RJ45 cable to a better location on the RHRS, with more slack and less likelihood of getting in the way of other people\
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**** Plotting adc0:event shows that the level comes out to ~28000, which is ~12% of the supposed range of the 18 bit ADCs
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* Check if something like int = 2 and conv = 0 is actually a more suitable gain setting
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*** Run number 4042 - 500, 800, 1000, 1400, 400, 1800, 2000, 2400, 400
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* Understand the nature of "saturation", why signals over 5V are suitable if the gain is low enough, and what non-linearities arise near saturation
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**** Plotting adc0:event shows again that we don't saturate - the peak value is just 140,000 now (for 2400 Level ~ 6 volts input signal)
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* Put all of the DAQ software into a [https://www.github.com/JeffersonLab JeffersonLab] repository and track it adequately
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* (JAPAN?) Develop a similar ramping function but to use a constant DAC value and systematically scan the gain settings to understand the linearity, starting points, and relative significance of Integrator and Conversion gains
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* Learn how to tweak and characterize QWeak ADCs (begin with RHRS QWeak ADCs)
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* Do the LHRS, Injector, and Counting House
 +
 
  
 
[[Category:DAQ_Testing]]
 
[[Category:DAQ_Testing]]

Latest revision as of 11:28, 30 July 2018

Back to Main Page >> DAQ Documentation Portal >> DAQ Testing >> DAQ Commissioning Notes

>> Next Day of Testing

July 27th, 2018 Testers: Cameron and Chandan

See Today's Meeting Notes

Goal

Cameron and Chandan learn how to test DAC and ADCs with Bob Michaels

Calibrate RHRS HAPPEX Timing Board (HAPTB ) 12 and 16 bit DAC

To calibrate the 12 and 16 bit DACs we:

  • Log into the RHRS ROC with telnet (see Network Map)
  • Set the DAC output level with the C code command setDACHAPTB(DAC#,Level#)
  • Read the DAC output level with a voltmeter
    • DAC# 1 = 12bit, 2 = 16 bit

Testing RHRS HAPPEX ADCs using 12bit DAC

  • To test an ADC channel
    • Set a specific ADC slot and channel number's gains in the Prex_ts.crl file (in ~/devices/crl/) and make with "makelist Prex_ts.crl ppc"
    • Run through several DAC values and ensure that the base and peak values (adcx#_#_b0 or p0) are not railed to minimum or maximum values
    • Reset the conversion and integrator gain values with functions
      • adc18_intgain(adcModule#,value#) - min = 3, max = 0
      • adc18_setconv(adcModule#,value#) - min = 0, max = 15
      • in Prex_ts.crl around lines 543 and 544 - inside a loop that sets every single ADC channel and gain in all DAQs
      • Set to lower net level first, and scan up
      • to see how high a gain can still read the peak 5V voltage from DAC at ~75% of saturation level
    • We are testing with 30Hz helicity flip rate (longest integration time, most likely to saturate, probably will be used for CREX)
    • Metrics - analyze a run's output with ~/adc18_ana/newrun run# numEvents# roc# slot#
  • RHRS "adcx2" according to tape label = first ADC on the left (of two options) of the 18bit ADC crate; address = 0 in ROC26 crate, name = adcx7 in ~/bpan18/pan/control.db
    • test by logging into HAPPEX7 via telnet and running int and conv gain settings (adcModule#=0) in there while CODA takes data in the background

To Do

  • Test ADCs and continue in todo list
  • Perfect and better justify parameters in Ramp testing function (and separate it out into a specific ramp-testing .crl file to avoid messing with the main Prex_ts.crl functionality)
  • Move the RJ45 cable to a better location on the RHRS, with more slack and less likelihood of getting in the way of other people\
  • Check if something like int = 2 and conv = 0 is actually a more suitable gain setting
  • Understand the nature of "saturation", why signals over 5V are suitable if the gain is low enough, and what non-linearities arise near saturation
  • Put all of the DAQ software into a JeffersonLab repository and track it adequately
  • (JAPAN?) Develop a similar ramping function but to use a constant DAC value and systematically scan the gain settings to understand the linearity, starting points, and relative significance of Integrator and Conversion gains
  • Learn how to tweak and characterize QWeak ADCs (begin with RHRS QWeak ADCs)
  • Do the LHRS, Injector, and Counting House
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