DAQ Meeting/20180802

• Editing .crl's to have Banks
  • Don't edit all of it at once, Banks and Headers can coexist, so going one step at a time is fine
  • |= means leave bits there alone, and add in some new bit
  • b0b444 is the begin of event header flag
  • Just add one bank at a time and it compiles just fine
  • %% just adds a } or { (which breaks logical C braces that any such code would be nested within)
• Adding in TS control flag
  • Diff the Prex_ts.crl and Prex.crl to see what ts control addition does
  • Ask Dave Abbott about what to do to get a preprocesessor directive in there to simplify life
• Update timing for FLEXIO in Injector DAQ
  • Jack Segal's webpage (~segal) has every user manual of every module (see phillips 795 gate generator manual, also available on Phillips website)
  • Program jumper may be placed in the wrong setting - it sits on the back of the module and selects a single output to send the delay
    • It looks like it is fine - currently set to disable (its on the back, there are 4 channels for remote programming that are all empty)
  • The

• Changed gate width and delay width on Delay Generator
  • 10 microsecond long width of "gate" delay signal and 150 nanosecond width of "delay" pulse (which starts at exactly the rising edge at the end of the delay signal)
  • See if delays show up in data correctly
• Check if STR7200 Scaler is behaving correctly
  • Ask Paul King
  • Reverse Engineer from QWeak analyzer