DAQ Meeting/20180802

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Logistic information

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Agenda

• Bob and Cameron : Check the gate and delayed T_Settle output to the FLEXIO, TI, and STR7200 Scaler, and make sure the injector studies later today go smoothly
• Bob and Cameron : Get Bank data structure incorporated in Prex_ts_banks.crl functionality

Minutes

• Cameron: Editing .crl's to have Banks
  • Notes from talking with Bob
    • Don't edit all of it at once, Banks and Headers can coexist, so going one step at a time is fine
    • |= means leave bits there alone, and add in some new bit
    • b0b444 is the begin of event header flag and should stay in for now
    • Just add one bank at a time and it compiles just fine
  • Talking to Dave Abbott, he says
    • %% (after "download"?) just adds a } or { (which breaks logical C braces that any such code would be nested within)
    • CRL language is just recipes for replacing lines with chunks of C code, and C code should be preferred over CRL language whenever possible
    • ${CODA_BIN}/ccrl is a compiler that doesn't make complicated .c output files for .crl's (though it also doesn't finish compiling), but at least it produces something readable for debugging purposes
  • Adding in TS control flag - Dave Abbott says
    • Diff the Prex_ts.c and Prex.c to see what ts control addition does
    • ts control is just setting a preprocessor directive in there to turn on some features, so it needs to be included at the top and not as a user string
  • I successfully changed Prex_ts.crl over to Prex_ts_banks.crl
    • The method of commenting I was using backfired, since apparently in C code block mode //# stuff actually gets interpreted by the crl compiler sometimes, especially if you use that block to comment out a *rol->dabuf++ = stuff line or put too many ######s
    • Anyway, I added in the C code version of the Bank open and Close statements
      • CBOPEN(BANK_ID_NUMBER,BT_UI4,VARIABLE_FOR_EVENT_NUMBER); and CBCLOSE;
        • where BANK_ID_NUMBER is an arbitrary number defined at the top of the .crl for referencing particular banks
        • BT_UI4 is a system variable defined elsewhere that gets defined as BT_UI4_ty after compilation
    • Compilation can be done
      • with the makelist *.crl ppc to generate the necessary *.o file
      • or with ${CODA_BIN}/ccrl compilation/c code conversion to generate a more readable .c file
  • Issues:
    • I had problems getting the comments to work correctly, as noted before, but I also had some other issues
      • so the removed header data writing lines were removed and should be added back in as some safe form of comment for consistency, as well as comments for other things I added in that are new, see Prex_ts_*_comments.crl
    • Putting any comments of any form, or putting the bank open and close inside the "dirty trick" that relies on a goto statement fails to compile
      • so the placement of the banks around that goto should be checked for logical equivalence with the prior header declaration
    • Putting the bank open and close around some places, particularly the end of the file at the QWeak ADC writing section was a bit weirder, probably something to do with some ifdefs needing the be independent of bank open and closes
      • so bank opens and closes around ifdefs were split up, one copy per ifdef option for the scalers, and sandwiched around the ifdef for QWeak ADCs, and their logical consistency needs to be checked
    • I haven't checked that the xfcedump output has the banks implemented correctly, but this should be easy enough to do
      • so I should make a new run with this configuration when other people aren't using adaq3 and see that the data looks good in xfcedump

• Cameron and Bob: Update timing for FLEXIO in Injector DAQ
  • Jack Segal's webpage (~segal) has every user manual of every module (see phillips 795 gate generator manual, also available on Phillips website)
  • Program jumper may be placed in the wrong setting - it sits on the back of the module and selects a single output to send the delay
    • It looks like it is fine - currently set to disable (its on the back, there are 4 channels for remote programming that are all empty)
  • Changed gate width and delay width on Delay Generator
    • 10 microsecond long width of "gate" delay signal and 150 nanosecond width of "delay" pulse (which starts at exactly the rising edge at the end of the delay signal)
    • Later in the day this delay was changed later in the day due to helicity errors
      • The delayed signal was bypassed, changing the delay into the FLEXIO from 10 microseconds to 0 and fixing the problem
      • This "fix" is not good and should be verified and set to behave as we actually want it to, probably requiring a much longer delay and some further testing
    • See if delays show up in data correctly (Run 4127 using Injector.crl)
  • Check if STR7200 Scaler is behaving correctly
    • Ask Paul King - emails were exchanged and a brief diagram was created, and it appears that the delay needs to be 8 helicity window, when we just set it to 1 window
    • Reverse Engineer from QWeak analyzer? It looks like it is behaving as intended, though JAPAN may need some help too

Testing

Today's testing