Difference between revisions of "DAQ Testing/20181106"
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== Results == | == Results == | ||
<gallery> | <gallery> | ||
| − | File: | + | File:Timing-Injector-TIR-ext.png|Timing Diagram, Injector, TIR ext mode |
| − | File: | + | File:Timing-Injector-TIR-CRL.png|Timing Diagram, Injector, TIR ext mode |
| − | File: | + | File:Timing-Injector-Vqwk-Gates.png|Timing Diagram, Injector, TIR ext mode |
| − | File: | + | File:Timing-Injector-SIS3801.png|Timing Diagram, Injector, TIR ext mode |
| − | File: | + | File:Timing-Injector-STR7200.png|Timing Diagram, Injector, TIR ext mode |
| − | File: | + | File:Timing-Injector-Flexio.png|Timing Diagram, Injector, TIR ext mode |
</gallery> | </gallery> | ||
Revision as of 13:36, 7 November 2018
Back to Main Page >> DAQ Documentation Portal >> DAQ Testing >> DAQ Commissioning Notes
Previous Day of Testing << >> Next Day of Testing
November 6th, 2018 Testers: Bob, Cameron
Goals
- Update Injector DAQ Timing Diagrams (see all in DAQ Layouts)
- TI (External gated standalone mode input)
- TI CRL outputs (overall busy out, vqwk wait, vqwk read, vqwk clear)
- QWeak ADCs gate
- SIS3801 Scaler
- STR7200 Scaler (needs spare)
- FLEXIO Scaler
Tests
TI ext standalone trigger mode (not receiving Trigger Supervisor trigger signal)
In normal mode the DAQ is triggered off of the trigger supervisor (TS) in the counting house, but in standalone mode (such as the Injector CODA configuration) it triggers off of channel 0 input
- Channel 0 is a twisted pair, takes Tstable and triggers the entire DAQ based off of this
- Tsettle's falling edge is chosen as the t=0 reference point for all diagrams (since it indicates the beginning of a new Helicity window)
- Tsettle has a glitch, where a substantial fraction of the signals are smaller in magnitude (from 40 us onward, for a given messed up pulse) - see here. Is this an issue? A symptom of a bigger problem? This NIM crate was found to have serious problems a few months ago, are they back?
- 500 us wide in standard running mode (currently used by Hall B runnning)
- Channel 0's Tstable is the complement of Tsettle and it's falling edge indicates when it is safe to begin integrating HEL dependent data
- 500 us after Tsettle (as expected)
- Tsettle's falling edge is chosen as the t=0 reference point for all diagrams (since it indicates the beginning of a new Helicity window)
- Timing Diagram, Injector, TIR ext mode
TI CRL outputs
The TI module can write to 8 bits via ROC (VXworks) commands. There are several signals written to these bits during a standard CODA readout list (CRL) execution, primarily for controlling the ADCs as they are being read out and monitored on the fly by the ROC and CODA. The injector TI module is governed by the ~/devices/crl/injector/Injector.crl CRL and is used for vetoing Vqwk gate signals.
- TI in standalone mode triggers on Channel 0 Tstable (see diagram above)
Results
Timing Diagram, Injector, TIR ext mode
Timing Diagram, Injector, TIR ext mode
Timing Diagram, Injector, TIR ext mode
Timing Diagram, Injector, TIR ext mode
Timing Diagram, Injector, TIR ext mode
Timing Diagram, Injector, TIR ext mode
