Difference between revisions of "DAQ Testing/20181106"

From PREX Wiki
Jump to navigationJump to search
Line 10: Line 10:
 
== Goals ==
 
== Goals ==
 
* Update Injector DAQ Timing Diagrams (see all in [[DAQ_Layouts#Injector_Timing_Diagram|DAQ Layouts]])
 
* Update Injector DAQ Timing Diagrams (see all in [[DAQ_Layouts#Injector_Timing_Diagram|DAQ Layouts]])
** TI (External standalone mode input)
+
** TI (External gated standalone mode input)
** TI CRL outputs (overall busy out, vqwk wait, vqwk read)
+
** TI CRL outputs (overall busy out, vqwk wait, vqwk read, vqwk clear)
 
** QWeak ADCs gate
 
** QWeak ADCs gate
 +
** SIS3801 Scaler
 +
** STR7200 Scaler (needs spare)
 +
** FLEXIO Scaler
  
 
== Tests ==
 
== Tests ==
 +
TI ext standalone trigger mode (not receiving Trigger Supervisor trigger signal)
 +
* Channel 0 is a twisted pair, takes Tstable and triggers the entire DAQ based off of this
 +
** Tsettle's falling edge is chosen as the t=0 reference point for all diagrams (since it indicates the beginning of a new Helicity window)
 +
*** 500 us wide in standard running mode (currently used by Hall B runnning)
 +
** Tstable is the complement of Tsettle and it's falling edge indicates when it is safe to begin integrating HEL dependent data
 +
*** 500 us after Tsettle (as expected)
 +
* [[:media:Timing-Injector-TIR-ext.PNG|Timing Diagram, Injector, TIR ext mode]]
  
 
== Results ==
 
== Results ==

Revision as of 13:20, 7 November 2018

Back to Main Page >> DAQ Documentation Portal >> DAQ Testing >> DAQ Commissioning Notes

Previous Day of Testing << >> Next Day of Testing

November 6th, 2018 Testers: Bob, Cameron

See Today's Meeting Notes

Goals

  • Update Injector DAQ Timing Diagrams (see all in DAQ Layouts)
    • TI (External gated standalone mode input)
    • TI CRL outputs (overall busy out, vqwk wait, vqwk read, vqwk clear)
    • QWeak ADCs gate
    • SIS3801 Scaler
    • STR7200 Scaler (needs spare)
    • FLEXIO Scaler

Tests

TI ext standalone trigger mode (not receiving Trigger Supervisor trigger signal)

  • Channel 0 is a twisted pair, takes Tstable and triggers the entire DAQ based off of this
    • Tsettle's falling edge is chosen as the t=0 reference point for all diagrams (since it indicates the beginning of a new Helicity window)
      • 500 us wide in standard running mode (currently used by Hall B runnning)
    • Tstable is the complement of Tsettle and it's falling edge indicates when it is safe to begin integrating HEL dependent data
      • 500 us after Tsettle (as expected)
  • Timing Diagram, Injector, TIR ext mode

Results

To Do