DAQ Testing/20181114

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Old-Example Timing Diagram, Injector, FLEXIO - Contains all Helicity Signals

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November 14th, 2018 Testers: Bob, Cameron, Ye Tian

See Today's Meeting Notes

Goals

Fix the timing in the SIS3801 so that it latches LNE before the present event's helicity information are read out, instead of whatever was going on before that did not match the diagram given in Old-Timing Diagram, Injector, SIS3801.

SIS3801 Scaler

Checking old settings, delayed Tsettle latch LNE

• Problem - when I originally checked the data I did not read the exact channel plugged into the SIS3801 input, mainly because I didn't want to unplug anything or taint the data being collected, and partly because there were available neighbouring channels in the 726 NIM-TTL level converter that some of the signals were going through.
  • Therefore I checked both the same way I did before and with taking the channel itself and plugging it into the scope (in case the wire was bad or something)
  • Result: The 726 NIM-TTL level translator is broken
    • Evidence: When two terminated cables are plugged into the level translator it behaves as was documented in previous testing

Results

• We changed the FLEXIO latch LNE to be delayed until after the prior event was read out, adding a new delayed Tsettle with a 100 us delay and 50 ns gate length (irrelevant).

To Do

• It turns out that the timing diagram for the SIS3801 appears to conflict with the readouts, in that it looks like the SIS3801 is reading the current event (like the FLEXIO has now been changed to be, when it is supposed to be reading the prior one.
• We should double check the old timing diagram and fix the delay if the drawing was drawn wrong, and figure out what is going on with the helicity information if the drawing is correct (since it seems to be behaving differently).