DAQ Testing/20181106

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November 6th, 2018 Testers: Bob, Cameron

Goals

Update Injector DAQ Timing Diagrams (see all in DAQ Layouts)
- TI (External gated standalone mode input)
- TI CRL outputs (overall busy out, vqwk wait, vqwk read, vqwk clear)
- QWeak ADCs gate
- SIS3801 Scaler
- STR7200 Scaler (needs spare)
- FLEXIO Scaler

Tests

TI ext standalone trigger mode (not receiving Trigger Supervisor trigger signal)

In normal mode the DAQ is triggered off of the trigger supervisor (TS) in the counting house, but in standalone mode (such as the Injector CODA configuration) it triggers off of channel 0 input

Channel 0 is a twisted pair, takes Tstable and triggers the entire DAQ based off of this
- Tsettle's falling edge is chosen as the t=0 reference point for all diagrams (since it indicates the beginning of a new Helicity window)
  - Tsettle has a glitch, where a substantial fraction of the signals are smaller in magnitude (from 40 us onward, for a given messed up pulse) - see here. Is this an issue? A symptom of a bigger problem? This NIM crate was found to have serious problems a few months ago, are they back?
  - 500 us wide in standard running mode (currently used by Hall B runnning)
- Channel 0's Tstable is the complement of Tsettle and it's falling edge indicates when it is safe to begin integrating HEL dependent data
  - 500 us after Tsettle (as expected)
Timing Diagram, Injector, TIR ext mode

TI CRL outputs

The TI module can write to 8 bits via ROC (VXworks) commands. There are several signals written to these bits during a standard CODA readout list (CRL) execution, primarily for controlling the ADCs as they are being read out and monitored on the fly by the ROC and CODA. The injector TI module is governed by the ~/devices/crl/injector/Injector.crl CRL and is used for vetoing Vqwk gate signals.

TI in standalone mode triggers on Channel 0 Tstable (see diagram above)
4 possible CRL set output bits (only one is in use), from the CRL code:
- Bit 8 = Busy Output = 0x80 = OPORT_BUSY - no signal in use
  - In the CRL it is set to true during the entire readout of each event (very long time)
  - On a scope the rising edge is 7.8 us after Tstable, and that Volts = 0 time is 675 us
  - Thus the falling edge starts at 500 +7.8 + 675 us = 1182.8 (just barely after the Read Vqwk signal, the precision on the 675 time is not high and probably these are coincident within a few CPU cycles)
- Bit 7 = Gate of Vqwks = 0x40 = OPORT_GATESOFF - twisted pair, blue Qbar, yellow Q
  - Gets passed to a gate (Tstable) + veto (this signal) generator and onto all Vqwk modules in the VME crate
  - Also gets passed into channel 32 of STR7200 scaler for counting
  - This signal is set to 1 in the CRL (meaning to stop reading or stop collecting Vqwk data) whenever the data is flushed due to a collection error or a start/stop/pause signal
  - Not a time-dependent signal, just on or off
- Bit 6 = Read Vqwks = 0x20 = OPORT_VQWKREAD - no signal in use
  - In the CRL it is set to enable readout and it is the dominant time chunk of the CRL readout routine
  - On a scope it looks like a slightly delayed Tstable whose rising edge is 112 us afer Tstable, but its width is a bit longer = 560 us - its falling edge is then at 612+560 = 1172 us after the t=0 Tsettle time
- Bit 5 = Wait for Vqwks = 0x10 = OPORT_VQWKWAIT - twisted pair, blue Qbar, white Q - doesn't get used in anything later on
  - In the CRL it makes the Vqwks wait for 30 (units, us?) and is set by the ROC for all Vqwks (??)
  - On a scope the falling edge is 112 us after Tstable = 612 us after Tsettle and it is 2 us in duration
Timing Diagram, Injector, TIR CRL mode

Vqwk Gates

The Vqwks are gated by a Tstable signal that can be vetoed by the CRL via TI write bit 7 - the width though appears to be very narrow (30 ns) - is this the intended outcome of a Gate + veto generator (with no delay)

The gate signal starts at the same time as Tstable and can be vetoed
Timing Diagram, Injector, Vqwk Gates

SIS3801 Scaler

The SIS3801 scaler counts every twisted pair plugged into it every time the Load Next Event (LNE) signal is read

The SIS3801 has an additional 4 NIM input bits (not standard scaler counter bits), of which one is the LNE
The LNE is the bottom left input bit channel - it is a delayed Tsettle
- Delayed Tsettle is obtained by taking the compliment of the Tstable helicity inputs to the NIM crate and then putting that Tsettle through a delay+gate generator
- The delay is 105 us and the gate width is 50 ns
The other three hold some copies of helicity information for double checking against the FLEXIO
- MPS in top left
- Tsettle in the Veto input bit - the top right of the 4 channels
- HEL + in the bottom right
Timing Diagram, Injector, SIS3801 mode