DAQ Testing/20181202

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December 2nd, 2018 Testers: Cameron

Goals

• Figure out how to read raw .dat files to find helicity signals by hand - decode raw data with a simple analyzer now

Reading Injector .dat Files in xcefdmp

See prior tests

Revisiting FLEXIO and SIS3801 LNE timing

Now I know where all copies of HEL+ are in raw data and what form they take

• SIS3801 scaler control bit - top 8 bits in each scaler word - HEL+ is the second from the highest bit - mask &0x40000000>>30
• SIS3801 scaler data - word 8, must mask top 8 bits to see it well, (probably) still interpretable otherwise though if you look in the lower bits - mask &0xfff
• FLEXIO - word 603, HEL+ is lowest bit - mask &0x1
• vqwk10_5 - word 555, 32 bit number that is easy to read - no mask

I used Bob's apar@adaq3:~/simpleAna code (modified to allow for injector non-bank analysis) to find the HEL+ signals and print them to the screen for a quick diagnostic of relative timing of signals

• Run 4685 - Injector run with no extra helicity signals plugged in anywhere
• Run 4686 - Injector run with the extra helicity signals plugged in (same as before, see above, but now no FLEXIO bit 15 used)

SIS3801 LNE timing

Per suggestion from Paul King I tested the timing again for Tsettle LNE and Tsettle LNE + 0.5us (in between Tsettle and the Helicity flip)

• Run 4687 - LNE == Tsettle cable (no delay generator) - SIS control bit lags the other signals by 1 window
• Run 4688 - LNE = Delayed by 0.5us Tsettle signal - SIS control bit lags the other signals by 1 window

FLEXIO LNE timing

Scanning to see where the FLEXIO is read out after ~Tstable

• Run 4689 - LNE = Tstable + 10 us (as in prior run 4674) - All signals line up nicely in SimpleAna, and xcefdmp, and Pan fails for a bunch of events (not all)!
• Run 4690 - LNE = Tstable + 10 us (double checking) - Same problems - looking closely at the helicity sequence it is apparent that sometimes the FLEXIO fails to update to the present window (but it does not lag behind systematically, it just fails to read correctly sometimes)
• Run 4691 - LNE = Tstable + 5 us - This acts like what I saw previously in run 4674 - The FLEXIO HEL+ signal leads the other data by 1 window (meaning we have latched it before reading in the current helicity window)
• Run 4692 - LNE = Tstable + 15 us - same problems as in + 10us cases above
• Run 4693 - LNE == Tsettle cable (no delay generator) - signal matches other HEL+ signals (like in benchmark run 4686) - this makes sense I think because the FLEXIO is latching on the following Tsettle, which is 1 us before the end of the event, in the same window of Tstable as was being integrated in benchmark run 4686
• Run 4694 - LNE == Tstable + 20 us - no HEL+ reading errors (as in 4689-4692), and the HEL+ matches the other signals (as in 4686) - this means that there is a ~15 us or so sensitive region centered around 5012.5 us after the beginning of Tsettle that we should avoid putting the FLEXIO LNE signal in (and this is probably heavily influenced by what is happening in the CRL - this timing could be different in the full PREX config, so we should be careful and measure that one too)
• Run 4695 - Another long run with the HEL+ signals plugged in (matching 4686), for bonus data and safety check

Results

The FLEXIO and SIS3801 behave as expected (I think). The SIS3801 lags the data being read out when using a Tsettle+marginal timing though, which feels un-useful compared to having it match the other signals being read out (as it has been this whole time otherwise).

To Do

• Incorporate Bob's Helicity sequence predictor to more carefully check miss-read FLEXIO bits and analyze (rather than judge data by eye) off-by-one errors with these helicity signals
• Figure out ET deadtime, use monitorGui and Bob's Helicity sequence predictor code
• Work with Ed Jastrzembski next week on Injector/Counting house TS synchronization