DAQ Testing/To-Do-Lists

11-6-2018

Check on health of the NIM crate and it's various output signals
Do the same thing for the Counting House
Check on/implement the helicity timing that is sent via the Counting House's Trigger Supervisor

We should look at file sizes as a function of time.
We should keep messing with the parameters.
We should take the TS busy out and use that in the scalers too (needs a non-binary ECL cable and translation).
We should use the java monitorGui to look at the data flow.

Go into the Injector (and CRL) and map out the timing.
Redo the tests with -q, -n, -r, and CHUNK size to see what affects the ET client analyzer's deadtime.

We can confidently use the Cavity BPM signals in the Parity DAQ for future tests now (we have verified ADC functionality for those channels).
A potentially confounding issue with SEE BPM B was resolved. There was a mirroring about the ym-xp axis that was fixed by swapping the wiring of yp and xm.

Verify the RAM stays by doing a hardware power cycle
Replicate battery replacement in all other ROCs to prevent this issue from reappearing (Cameron has the batteries)
Replace the HAPTB DAC to TI module twisted pair connection
Add HAPPEX Timing Board to Injector
Test all ADCs in Injector
Make a bank for all ADCs

Perfect and better justify parameters in Ramp testing function
Check if something like int = 2 and conv = 0 is actually a more suitable gain setting for HAPPEX ADCs
Put all of the DAQ software into a JeffersonLab repository and track it adequately
Develop a similar ramping function but to use a constant DAC value and systematically scan the gain settings to understand the linearity, starting points, and relative significance of Integrator and Conversion gains for HAPPEX ADCs
Do the QWeak ADCs in the Injector and verify issues with the ones in the Counting House + figure out how to test the Counting House HAPPEX ADCs
Make a map of all channels and logic
Characterize and test all scaler channels

Perfect and better justify parameters in Ramp testing function (and separate it out into a specific ramp-testing .crl file to avoid messing with the main Prex_ts.crl functionality)
Move the RJ45 cable to a better location on the RHRS, with more slack and less likelihood of getting in the way of other people\
Check if something like int = 2 and conv = 0 is actually a more suitable gain setting
Understand the nature of "saturation", why signals over 5V are suitable if the gain is low enough, and what non-linearities arise near saturation
Put all of the DAQ software into a JeffersonLab repository and track it adequately
(JAPAN?) Develop a similar ramping function but to use a constant DAC value and systematically scan the gain settings to understand the linearity, starting points, and relative significance of Integrator and Conversion gains
Learn how to tweak and characterize QWeak ADCs (begin with RHRS QWeak ADCs)
Do the LHRS, Injector, and Counting House

Test ADCs and continue in todo list
Perfect and better justify parameters in Ramp testing function (and separate it out into a specific ramp-testing .crl file to avoid messing with the main Prex_ts.crl functionality)
Move the RJ45 cable to a better location on the RHRS, with more slack and less likelihood of getting in the way of other people\
Check if something like int = 2 and conv = 0 is actually a more suitable gain setting
Understand the nature of "saturation", why signals over 5V are suitable if the gain is low enough, and what non-linearities arise near saturation
Put all of the DAQ software into a JeffersonLab repository and track it adequately
Develop a similar ramping function but to use a constant DAC value and systematically scan the gain settings to understand the linearity, starting points, and relative significance of Integrator and Conversion gains
Learn how to tweak and characterize QWeak ADCs (begin with RHRS QWeak ADCs)
Do the LHRS, Injector, and Counting House