DAQ Hardware HAPTB

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Happex Timing board - programmable gate generator and official controller of Happex ADCs

The Happex Timing Board (HAPTB) was developed at JLab and has been used in the various PVES experiments, primarily as the trigger controller for the Happex ADCs, but now also as the controller for the VQWK ADCs (using the GMN output, which gives the same timing as what the HAPPEX ADCs get from their ribbon cable connection).

The timing board is very stable and can create gates of up to 163.84 ms long with sub microsecond (tens of nanoseconds for ~8ms gates) precision. The time units native to the timing board come in multiples of 2.5 us, so keep that in mind when entering in inputs (and recall that the VQWK ADCs have units of 2us, which are 4/5 commensurate).

VME HW address

The standard Happex Timing Board VME address is set with bits on the board, with the numbers going in reverse order to the standard interpretation. The standard address value is 0xb0b0 (and the last 0 digit isn't accessible to the set of bits on the board itself, so it is practically speaking just b0b, which looks like 101100001011 in binary going from left to right, where 1 is up and 0 is down on these boards).

Trigger

The trigger for the timing board is what defines the T=0 against which everything else is determined. The standard input for the trigger is a LEMO connection female input port labelled "TRIG IN". There is also a fiber input, but it is preferred to use the LEMO one as it can be placed in a scope more readily to check its timing. The logic of the TRIG IN LEMO signal must be standard TTL.

Jumpers for TTL or TTL-bar logic

There is a pair of jumpers that determines whether to use normal or inverted logic standard - these jumpers are located next to the FPGA chip on the board, approximately in the center of the board - when the upper (closer to the FPGA chip) jumper is closed (black jumper attached) then the logic standard is inverted, and when the lower of the two jumpers is closed it will be standard TTL logic (preferred).

Standard DAQ trigger

The usual trigger for Parity DAQ running is the MPS signal. We use the falling edge of Tsettle (the beginning of the MPS pulse and the falling edge of the MPS-bar signal) to trigger the Trigger Supervisor (TS) and begin the ROC's CRL trigger routine. We also would like to use this MPS pulse to trigger the Happex Timing board, though there are some limitations to getting exact timing out of the board. Because the Timing Board is running software and was designed with Tsettle times in mind, there is a built in 22.5 us minimum delay that the board waits from receiving the trigger to beginning its output (GMN) routine.

GMN ADC trigger

After the trigger has been set up for the timing board the user can determine what the relative time of the output ADC gate signal (GMN) should be. Using the HAPTB libraries (~/devices/timebrd/HAPTB_util.o) loaded on a vxworks ROC the user can set the Ramp Delay and Integrate time using

setTimeHAPTB(RampDelay,IntTime)

where RampDelay is an integer from 0-65535 and the effect is to add RampDelay*2.5 us after the initial built in 22.5 us delay before beginning the GMN signal, and the IntTime value is also an integer from 0-65535 whose effect is to add IntTime*2.5 us after an initial built in 5 us integration time to hold this gate in the true state. The integration gate time length is only important if the timing board is being used to opperate the HAPPEX ADCs, in which case its start time and length define the integration window for the HAPPEX ADCs, or in the case that the user needs a gate generated and defined for a certain amount of time. In VQWK ADC operation the gate can be < us in length, so a IntTime setting of 0 is sufficient. The preferred output from the timing board is the differential ECL (dECL) twisted pair output near the bottom in the 3rd output place, labelled "GMN2". These values can be obtained from the vxworks command line (with HAPTB_util.o loaded) with the commands getIntTimeHAPTB() and getRampDelayHAPTB().