DAQ Testing/20180727

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July 27th, 2018 Testers: Cameron and Chandan

Goal: Cameron and Chandan learn how to test DAC and ADCs with Bob Michaels

Calibrate RHRS HAPPEX Timing Board (HAPTB ) 12 and 16 bit DAC

To calibrate the 12 and 16 bit DACs we:

• Log into the RHRS ROC with telnet (see Network Map)
• Set the DAC output level with the C code command setDACHAPTB(DAC#,Level#)
• Read the DAC output level with a voltmeter
  • DAC# 1 = 12bit, 2 = 16 bit

Testing RHRS HAPPEX ADCs using 12bit DAC

• To test an ADC channel
  • Set a specific ADC slot and channel number's gains in the Prex_ts.crl file (in ~/devices/crl/) and make with "makelist Prex_ts.crl ppc"
  • Run through several DAC values and ensure that the base and peak values (adcx#_#_b0 or p0) are not railed to minimum or maximum values
  • Reset the conversion and integrator gain values with functions
    • adc18_intgain(adcModule#,value#) - min = 3, max = 0
    • adc18_setconv(adcModule#,value#) - min = 0, max = 15
    • in Prex_ts.crl around lines 543 and 544 - inside a loop that sets every single ADC channel and gain in all DAQs
    • Set to lower net level first, and scan up
    • to see how high a gain can still read the peak 5V voltage from DAC at ~75% of saturation level
  • We are testing with 30Hz helicity flip rate (longest integration time, most likely to saturate, probably will be used for CREX)
  • Metrics - analyze a run's output with ~/adc18_ana/newrun run# numEvents# roc# slot#
• RHRS "adcx2" according to tape label = first ADC on the left (of two options) of the 18bit ADC crate; address = 0 in ROC26 crate, name = adcx7 in ~/bpan18/pan/control.db
  • test by logging into HAPPEX7 via telnet and running int and conv gain settings (adcModule#=0) in there while CODA takes data in the background

To Do

• Test ADCs and continue in todo list
• Perfect and better justify parameters in Ramp testing function (and separate it out into a specific ramp-testing .crl file to avoid messing with the main Prex_ts.crl functionality)
• Move the RJ45 cable to a better location on the RHRS, with more slack and less likelihood of getting in the way of other people\
• Check if something like int = 2 and conv = 0 is actually a more suitable gain setting
• Understand the nature of "saturation", why signals over 5V are suitable if the gain is low enough, and what non-linearities arise near saturation
• Put all of the DAQ software into a JeffersonLab repository and track it adequately
• (JAPAN?) Develop a similar ramping function but to use a constant DAC value and systematically scan the gain settings to understand the linearity, starting points, and relative significance of Integrator and Conversion gains
• Learn how to tweak and characterize QWeak ADCs (begin with RHRS QWeak ADCs)
• Do the LHRS, Injector, and Counting House