DAQ Testing/20190430
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April 30th, 2019 Testers: Cameron Clarke, Caryn Palatchi, Paul King
Goals
- Finalize timing of Parity DAQ
- Include run-time scripts in CEDIT config
- Plan/code up the Tune Beam VQWK Gate scanning (incorporate scalers and HAPPEX ADCs too?)
- Add Inj DAQ to sync check system
- Add batteries for pedestal studies
Add Batteries and finalize maps
- Cameron and Caryn added batteries into the CH and INJ
- 3 Volts in INJ ADC_11_06, INJ ADC_00_07, -1.5 Volts in CH ADC_05_02
- Put Beam Sync from Patch Panel into CH ADC_05_01, and BPM trig signal into CH ADC_05_00
- Put IOCse9 BPM 12 wires 002, 003, 004, 005 ( = xp, xm, yp, ym), BPM 14 wires 001, 011, 012, 013 (same ordering), and BPM 08 wires 006, 007, 008, 009 (all linac style) into CH wires that are plugged into ADCs
- Plugged BPM 002 into INJ scaler V2F signals (needs some clock software work)
- Another INJ ADC_0 bpm should be added and another V2F bpm should be added too
Run List
- 2102 - test new maps, errors with pattern phase counter (and V2F clock missing and NSamples wrong)
- 2103-2106 - same errors
- 2107 - Fixed the pattern phase
- 2108 - Longer run, still fixed
