DAQ Hardware STR7200

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Injector Timing Diagram 11/6/2018

  • See DAQ_Testing/20181106 for notes on the timing of the STR7200 scaler in the injector (at that time)
  • Note that there is not currently known backup and one should be found or the scaler should be swapped for a more common one

From Paul King - Aug 2, 2018

Regarding the circuit at the Injector DAQ and in particular the STR7200 purpose and setup

The design of the circuit was to have the helicity bits latched at the beginning of the TStable window, so that when the VQWKs were read at the end the helicity bits should correspond the to VQWK data. This should result in a helicity delay of 8 windows (or whatever the hel board was using) instead of a delay shifted by one window from what the hel board was using.

The STR7200 is used to cross-check that the FLEXIO input register reading is current, by counting the TStable transitions and pattern-sync transitions. It should also give a hardware counter of what is the event number within the pattern, by clearing a TStable counter on the pattern-sync transitions.

The "TStable counter" signal should probably be a copy of the "beginning of TStable" signal whcih is also used to latch the FLEXIO, but it might be a copy of the "end of Tstable" signal which is used as the LNE for the 3801 scalers.

It should be a short duration signal for all three. Part of the use of the GG was to just make a narrow pulse from the leading-edge of the TStable, but the delay was also there to ensure we were latching the FLEXIO well after it was readout fromt he previous event (it gets read at the very start of the CRL, so the delay may not be needed, but it should be a short signal).

The "Pattern start counter" signal should be the logical AND of the "TStable counter" signal and the full duration pattern sync signal from the helicity board.

I think the "ADC gate counter" was a direct copy of the gate signal sent to the VQWK modules. This was used when we were potentially going to use the HAPPEX timing board oversampling during PREX-1, so that it would be possible to count the oversamples within each helicity window.

Since we aren't using that mode, we don't need to keep the Ch.16 input and the clearing signal derived from the TStable signal.

  • STR7200 input channels:
    • Ch. 0 - TStable counter
    • Ch. 1 - Pattern start counter
    • Ch. 2 - ADC gate counter
    • Ch. 8 - Copy of TStable counter (cleared by Pattern start)
    • Ch. 16 ADC gate within TStable (NOT NEEDED IN PREX-2)
  • Control inputs:
    • 4th input - Copy of the pattern start counter, used to clear input channels 8-15.
    • 6th input (plugged into 5 in the actual module) - Copy of TStable start signal, used to clear input channels 16-23. (NOT NEEDED IN PREX-2)