DAQ Testing/20190501

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May 1st, 2019 Testers: Cameron Clarke

Goals

• Finalize timing of Parity DAQ
• Include run-time scripts in CEDIT config
• Plan/code up the Tune Beam VQWK Gate scanning (incorporate scalers and HAPPEX ADCs too?)
• Add Inj DAQ to sync check system

Timing of VQWK Gate

• VQWK ramp delay settings don't have the range needed to achieve the tune beam pulse scanning
• We can use some reliable programmable gate generator to do this instead of vqwk+physical gate generator
• Additional HAPTB in CH (either a second one in CH crate, a new one in TS crate, or jettisoning the HAPPEX ADCs) and INJ should work
  • To add a new one in TS crate requires adding the socket server to that ROC
  • To add a new one in CH crate requires editing code to allow for two in one crate (and killing Evan's digital BCM)
  • To add a new one in the injector probably requires adding a socket server to that ROC and finding a spot in the crate
• Another goal is to cut out the wait of the internal VQWK gate delay (some 20 us to be safe, we should study the effect of this timing too...) by putting the HAPTB start time at the beginning of TSettle and then timing when it should have the ADC gate be sent in order for the integration start to line up with TStable (in tune beam mode and with a TStable signal plugged in)

STR7200 spare

Bob knows a guy in Hall B, and Paul may have a spare from QWeak

Run-time scripts in CEDIT config

• Paul showed Sangwha and Robert how to configure the scripts and we decided to eventually use prestart, go, and end wrapper scripts
• The fast logger needs some work and needs to be killed at the end of each run
• We need to resurrect the log-GUI for PREX