DAQ Testing/20181106

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Example Timing Diagram, Injector, FLEXIO - Contains all Helicity Signals

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November 6th, 2018 Testers: Bob, Cameron

See Today's Meeting Notes

Goals

  • Update Injector DAQ Timing Diagrams (see all in DAQ Layouts)
    • TI (External gated standalone mode input)
    • TI CRL outputs (overall busy out, vqwk wait, vqwk read, vqwk clear)
    • QWeak ADCs gate
    • SIS3801 Scaler
    • STR7200 Scaler (needs spare)
    • FLEXIO Scaler

Tests

All of these tests were performed on 11/6/2018 with semi-stable beam running at ~30Hz into Hall B, with Tstable set to 500us - the data from the very long run is stored in run number 4568 and was taken with the Injector CRL and Injector CODA configuration.

Bob Commentary

TI ext standalone trigger mode (not receiving Trigger Supervisor trigger signal)

In normal mode the DAQ is triggered off of the trigger supervisor (TS) in the counting house, but in standalone mode (such as the Injector CODA configuration) it triggers off of channel 0 input

  • Channel 0 is a twisted pair, takes Tstable and triggers the entire DAQ based off of this
    • Tsettle's falling edge is chosen as the t=0 reference point for all diagrams (since it indicates the beginning of a new Helicity window)
      • Tsettle has a glitch, where a substantial fraction of the signals are smaller in magnitude (from 40 us onward, for a given messed up pulse) - see here. Is this an issue? A symptom of a bigger problem? This NIM crate was found to have serious problems a few months ago, are they back?
      • 500 us wide in standard running mode (currently used by Hall B runnning)
    • Channel 0's Tstable is the complement of Tsettle and it's falling edge indicates when it is safe to begin integrating HEL dependent data
      • 500 us after Tsettle (as expected)
  • Timing Diagram, Injector, TIR ext mode

TI CRL outputs

The TI module can write to 8 bits via ROC (VXworks) commands. There are several signals written to these bits during a standard CODA readout list (CRL) execution, primarily for controlling the ADCs as they are being read out and monitored on the fly by the ROC and CODA. The injector TI module is governed by the ~/devices/crl/injector/Injector.crl CRL and is used for vetoing Vqwk gate signals.

  • TI in standalone mode triggers on Channel 0 Tstable (see diagram above)
  • 4 possible CRL set output bits (only one is in use), from the CRL code:
    • Bit 8 = Busy Output = 0x80 = OPORT_BUSY - no signal in use
      • In the CRL it is set to true during the entire readout of each event (very long time)
      • On a scope the rising edge is 7.8 us after Tstable, and that Volts = 0 time is 675 us
      • Thus the falling edge starts at 500 +7.8 + 675 us = 1182.8 (just barely after the Read Vqwk signal, the precision on the 675 time is not high and probably these are coincident within a few CPU cycles)
    • Bit 7 = Gate of Vqwks = 0x40 = OPORT_GATESOFF - twisted pair, blue Qbar, yellow Q
      • Gets passed to a gate (Tstable) + veto (this signal) generator and onto all Vqwk modules in the VME crate
      • Also gets passed into channel 32 of STR7200 scaler for counting
      • This signal is set to 1 in the CRL (meaning to stop reading or stop collecting Vqwk data) whenever the data is flushed due to a collection error or a start/stop/pause signal
      • Not a time-dependent signal, just on or off
    • Bit 6 = Read Vqwks = 0x20 = OPORT_VQWKREAD - no signal in use
      • In the CRL it is set to enable readout and it is the dominant time chunk of the CRL readout routine
      • On a scope it looks like a slightly delayed Tstable whose rising edge is 112 us afer Tstable, but its width is a bit longer = 560 us - its falling edge is then at 612+560 = 1172 us after the t=0 Tsettle time
    • Bit 5 = Wait for Vqwks = 0x10 = OPORT_VQWKWAIT - twisted pair, blue Qbar, white Q - doesn't get used in anything later on
      • In the CRL it makes the Vqwks wait for 30 (units, us?) and is set by the ROC for all Vqwks (??)
      • On a scope the falling edge is 112 us after Tstable = 612 us after Tsettle and it is 2 us in duration
  • Timing Diagram, Injector, TIR CRL mode

Vqwk Gates

The Vqwks are gated by a Tstable signal that can be vetoed by the CRL via TI write bit 7 - the width though appears to be very narrow (30 ns) - is this the intended outcome of a Gate + veto generator (with no delay)

SIS3801 Scaler

The SIS3801 scaler counts every twisted pair plugged into it every time the Load Next Event (LNE) signal is read

  • The SIS3801 has an additional 4 NIM input bits (not standard scaler counter bits), of which one is the LNE
  • The LNE is the bottom left input bit channel - it is a delayed Tsettle
    • Delayed Tsettle is obtained by taking the compliment of the Tstable helicity inputs to the NIM crate and then putting that Tsettle through a delay+gate generator
    • The delay is 105 us and the gate width is 50 ns
  • The other three hold some copies of helicity information for double checking against the FLEXIO
    • MPS in top left
    • Tsettle in the Veto input bit - the top right of the 4 channels
    • HEL + in the bottom right
  • Timing Diagram, Injector, SIS3801 mode

STR7200 Scaler

The STR7200 scaler counts several redundant channels

  • Channel 0 is the latch to read (according to Paul King's documentation - here), and is a "Tstable counter"
    • It is standard Tstable
  • Channel 1 is the "Pattern Start Counter"
    • On a scope this signal seems off
    • It is some logical combination of standard MPS/QRT/MultiSync + Tstable
    • It is delayed from Tsettle by 37.5 ns and lasts for 100ns (double check this number, may be off, and maybe the input signals aren't operating correctly, or the logic module is messed up?)
  • Channel 2 is the "ADC Gate Counter"
    • Which is a 150ns long, 105 us delayed Tsettle signal (like what is used as the trigger LNE in SIS3801)
    • It isn't counting the actual ADC gate signal though... misnomer? This should be checked again as well to make sure the correct signals were read by me and that the correct signals are plugged in to the right channels
  • Channel 8 is a "Copy of Tstable Counter"
    • It is a direct copy of Tstable
  • Channel 16 is a "ADC gate within Tstable counter" but there is nothing plugged into it - Paul says it is not needed in Prex II
  • Channel 32 currently has the 5th bit out from the TI module plugged in, but this is not necessary (per Paul)
  • "Control Input 4" is a copy of the Patter Counter - CI4 is used to clear out channels 8-15 but none of them are in use
  • "Control Input 6" (is currently plugged into channel 5, but there is an intermediate ground cable - misnamed in Paul's documentation?) is a copy of Tstable start signal, used to clear the input channel 16-23 but none of them are in use
    • It is a direct copy of Tstable
  • Timing Diagram, Injector, STR7200

FLEXIO Scaler

The FLEXIO scaler is used to count all of the helicity related information in 4 input channels, with Tstable used to latch

  • Channel 0 = HEL+
  • Channel 1 = HEL-
  • Channel 2 = MPS/QRT/MultiSync
  • Channel 4 = Pair Sync
  • All channels are the standard helicity information with no surprises
  • Timing Diagram, Injector, FLEXIO

Results

  • The timing has been determined from the CRL and from measuring all of the signals on a scope that are going into the TI, Vqwks, and SIS3801, STR7200 and FLEXIO scalers.
  • Diagrams are linked here (and should probably be uploaded again with date/time stamps to avoid version control errors in the wiki framework).

Issues

  • There are several issues:
    • Very close timings on the order of 10s of nano seconds that look questionable
    • Some of the logical combinations (Pattern Start Counter in STR7200, Vqwk Gate) look different than what I expect
    • The timing for the Delayed Tsettle LNE for the SIS3801 is not set to any specific value but happens to work (should be decided upon for general HEL flip rates, etc.)
    • The STR7200 Channel 2 "ADC Gate Counter" is not counting ADC gates (I think - should be double checked)
    • The Tsettle signal has a wiggle that starts at 40 us after its falling edge, but only sometimes (maybe when the QRT signal is given and it draws too much current??)
    • The Vqwk Tsettle gate (post-vetoed signal) appears different than a standard Tsettle, and is extrememly narrow - 30 ns

Timing Diagrams

To Do

  • Check on issues listed above
  • Check on health of the NIM crate and it's various output signals
  • Do the same thing for the Counting House
  • Check on/implement the helicity timing that is sent via the Counting House's Trigger Supervisor

comments

from Bob

1. TIR-CRL: Busy Out and Vqwk Read are inverted. NIM-true is <-0.8V. See also my drawing http://userweb.jlab.org/~rom/daq/injector_helicity.png

2. SIS3801 scaler timing and the FLEXIO strobe both look good. We need to check the relationship of the helicity-related bits from SIS3801 to the same from the FLEXIO. They need to be in lock-step agreement.

3. It looks like the VQWK gates come at the end of T_settle, and the readout starts 112 usec later. This is fine if the integration of a next pulse can occur while a readout is occuring. I suppose the frontend integration is decoupled from the data buffer, as long as the integration occurs well before we try to read data. We can check the VQWK user manual and ask Paul, but another test I suggest, using the CH config, is to send a random-jumping DAC value into both a VQWK and a HAPPEX ADC. Since I know how the HAPPEX ADCs work, this will confirm how the VQWK adcs work and show that they are in synch. If all that is fine, it implies that the VQWK data belongs to the previous helicity window, i.e. the one prior to where it is being read, which I think is what we want. T

4. We should discuss your "issues" in person. Timings that are in excess of 20 nsec are ok for signals that are expected to be stable. But microsec is better. We have gate generators, so we can fix this if necessary. Also, wiggles are worrisome, but generally the electronics triggers on leading edges (False to True) except for Veto logic which should be stable during the time. If a wiggles crosses the NIM-logic threshold it's bad.