Difference between revisions of "DAQ Testing/20190429"
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** Instead of using the Happex Timing board to generate gates and instead of using copies of Tsettle/Tstable for LNE gates Cameron made gate generators that are narrow pulses at those times to send as the signals to the CH and HRS DAQs (see last few pages of notes linked above). | ** Instead of using the Happex Timing board to generate gates and instead of using copies of Tsettle/Tstable for LNE gates Cameron made gate generators that are narrow pulses at those times to send as the signals to the CH and HRS DAQs (see last few pages of notes linked above). | ||
| + | == DAQ Updates April 29th == | ||
| + | |||
| + | Paul and Cameron traced the signals in the Parity Injector DAQ and made changes to the cabling and corrected the timing of several signals (see https://prex.jlab.org/wiki/index.php/DAQ_Testing/20190429) | ||
| + | |||
| + | * We fixed the pattern and MPS counter signal of the STR 7200 scaler (moved it in time to match the FLEXIO LNE) so they will count properly (no multiple counting now) and removed some superfluous signals that were being put into it (and MPS counter is now the vetoed VQWK gate signal). | ||
| + | * The SIS3801 LNE was moved to be at 10us after Tsettle (instead of 105 us after, which is bad when the TSettle window is <105us as it is for the current 120Hz running). | ||
| + | * Cleaned up a lot of old cabling and simplified paths/removed unread things from SIS3801 and STR 7200. | ||
| + | |||
| + | We did no change anything in the FLEXIO timing or in the VQWK timing | ||
| + | |||
| + | See: https://logbooks.jlab.org/entry/3680680 | ||
| + | |||
| + | === Run List === | ||
| + | |||
| + | * 2094 - started in original DAQ state, ended with MPS and PAT counters changed | ||
| + | * 2095 - MPS and PAT counter updated to read correctly to remove multiple counting, MPS && signal == FLEXIO LNE input signal | ||
| + | * 2096 - 2097 - more updates, ADC gate counter changed to be the VQWK (TI vqwk erro vetoed) LNE signal now, 2097 updates to not double pulse | ||
| + | * 2098 - Edited STR 7200 read signals | ||
| + | * 2099 - Changed SIS3801 LNE to be at 10us after TSettle | ||
| + | * 2100 - Test all INJ changes | ||
| + | * 2101 - Test all INJ changes in PREX_ALL mode | ||
== Misc Notes == | == Misc Notes == | ||
Latest revision as of 17:35, 29 April 2019
Back to Main Page >> DAQ Documentation Portal >> DAQ Testing >> DAQ Commissioning Notes
Previous Day of Testing << >> Next Day of Testing
April 29th, 2019 Testers: Cameron Clarke
Goals
- Finalize timing of Parity DAQ
- Include run-time scripts in CEDIT config
- Plan/code up the Tune Beam VQWK Gate scanning (incorporate scalers and HAPPEX ADCs too?)
- Add Inj DAQ to sync check system
DAQ Status after updating on April 10th
- APEX
- The DAQ point to point map from APEX running is documented here.
- The GMN2 signal was too late and the VQWK ADCs integrated into the subsequent TSettle window inappropriately, also see Caryn's note here which includes Beam Sync (relevant for moving to beam synched HelBoard settings).
- Modifications on April 10th
- Instead of using the Happex Timing board to generate gates and instead of using copies of Tsettle/Tstable for LNE gates Cameron made gate generators that are narrow pulses at those times to send as the signals to the CH and HRS DAQs (see last few pages of notes linked above).
DAQ Updates April 29th
Paul and Cameron traced the signals in the Parity Injector DAQ and made changes to the cabling and corrected the timing of several signals (see https://prex.jlab.org/wiki/index.php/DAQ_Testing/20190429)
- We fixed the pattern and MPS counter signal of the STR 7200 scaler (moved it in time to match the FLEXIO LNE) so they will count properly (no multiple counting now) and removed some superfluous signals that were being put into it (and MPS counter is now the vetoed VQWK gate signal).
- The SIS3801 LNE was moved to be at 10us after Tsettle (instead of 105 us after, which is bad when the TSettle window is <105us as it is for the current 120Hz running).
- Cleaned up a lot of old cabling and simplified paths/removed unread things from SIS3801 and STR 7200.
We did no change anything in the FLEXIO timing or in the VQWK timing
See: https://logbooks.jlab.org/entry/3680680
Run List
- 2094 - started in original DAQ state, ended with MPS and PAT counters changed
- 2095 - MPS and PAT counter updated to read correctly to remove multiple counting, MPS && signal == FLEXIO LNE input signal
- 2096 - 2097 - more updates, ADC gate counter changed to be the VQWK (TI vqwk erro vetoed) LNE signal now, 2097 updates to not double pulse
- 2098 - Edited STR 7200 read signals
- 2099 - Changed SIS3801 LNE to be at 10us after TSettle
- 2100 - Test all INJ changes
- 2101 - Test all INJ changes in PREX_ALL mode
Misc Notes
- In order to ensure that the cedit configs are reflected in translated databases look around in here:
/adaqfs/home/apar/coda26/cool/parity/config/Control/ALL_PREX/Processes
