DAQ Testing/20190429

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April 29th, 2019 Testers: Cameron Clarke

Goals

• Finalize timing of Parity DAQ
• Include run-time scripts in CEDIT config
• Plan/code up the Tune Beam VQWK Gate scanning (incorporate scalers and HAPPEX ADCs too?)
• Add Inj DAQ to sync check system

DAQ Status after updating on April 10th

• APEX
  • The DAQ point to point map from APEX running is documented here.
  • The GMN2 signal was too late and the VQWK ADCs integrated into the subsequent TSettle window inappropriately, also see Caryn's note here which includes Beam Sync (relevant for moving to beam synched HelBoard settings).
• Modifications on April 10th
  • Instead of using the Happex Timing board to generate gates and instead of using copies of Tsettle/Tstable for LNE gates Cameron made gate generators that are narrow pulses at those times to send as the signals to the CH and HRS DAQs (see last few pages of notes linked above).

Misc Notes

• In order to ensure that the cedit configs are reflected in translated databases look around in here:

/adaqfs/home/apar/coda26/cool/parity/config/Control/ALL_PREX/Processes