Difference between revisions of "TEDf-VQWK-Testing"

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Line 9: Line 9:
 
** [https://ace.phys.virginia.edu:80/HAPPEX/3619 HAPLOG 3619] describes BPM 8 test with new ADC in CH crate
 
** [https://ace.phys.virginia.edu:80/HAPPEX/3619 HAPLOG 3619] describes BPM 8 test with new ADC in CH crate
 
** run 1233 and 1234 were used to test (run 1233 had address conflict, so ignore)
 
** run 1233 and 1234 were used to test (run 1233 had address conflict, so ignore)
−
* Run 1655 - A board that was laying around, board 26  
+
* Run 1655 - test '''ADC 26'''
 
** [[:media:1655-Plots-ADC-26-Good.pdf|Plots]]
 
** [[:media:1655-Plots-ADC-26-Good.pdf|Plots]]
 
** It works
 
** It works
Line 15: Line 15:
 
** [[:media:1656-Plots-ADC-20-Bad.pdf|Plots]]
 
** [[:media:1656-Plots-ADC-20-Bad.pdf|Plots]]
 
** Top 4 channels are bad, as seen in CH crate data
 
** Top 4 channels are bad, as seen in CH crate data
−
* Run 1657 - test ADC 15, the one with the strangely wired and tied on Op Amp
+
* Run 1657 - test '''ADC 15''', the one with the strangely wired and tied on Op Amp
 
** [[:media:1657-Plots-ADC-15-Good.pdf|Plots]]
 
** [[:media:1657-Plots-ADC-15-Good.pdf|Plots]]
 
** Works
 
** Works
−
* Run 1658 - test ADC 37 - ISU board that has recently had new channels go bad on it
+
* Run 1658 - test '''ADC 37''' - ISU board that has recently had new channels go bad on it
 
** [[:media:1658-Plots-ADC-37-Bad.pdf|Plots]]
 
** [[:media:1658-Plots-ADC-37-Bad.pdf|Plots]]
 
** Bad channels 2, 3, 4
 
** Bad channels 2, 3, 4
Line 24: Line 24:
 
** Channel 3 works only in positive voltage range
 
** Channel 3 works only in positive voltage range
 
** No Japan error codes are reported
 
** No Japan error codes are reported
−
* Run 1659 - test ADC 32 - used wrong HW address, no ACC light blinking and many VQWK read errors on telnet session
+
* Run 1659 - test '''ADC 32''' - used wrong HW address, no ACC light blinking and many VQWK read errors on telnet session
 
* Run 1660-1662 - test ADC 32 - corrected HW address (needs to be 0x8400)
 
* Run 1660-1662 - test ADC 32 - corrected HW address (needs to be 0x8400)
 
** [[:media:1660-Plots-ADC-32-Bad.pdf|Plots for first 6 channels tested]]
 
** [[:media:1660-Plots-ADC-32-Bad.pdf|Plots for first 6 channels tested]]
Line 33: Line 33:
 
*** I started a new run to clear read error messages, that didn't fix, so I rebooted, and after rebooting the data is clear - no signal/analog output from ADC channels
 
*** I started a new run to clear read error messages, that didn't fix, so I rebooted, and after rebooting the data is clear - no signal/analog output from ADC channels
 
** I removed the board and marked it as dead
 
** I removed the board and marked it as dead
−
* Run 1663 - test ADC 33 - ISU backup board
+
* Run 1663 - test '''ADC 33''' - ISU backup board
 
** [[:media:1663-Plots-ADC-33-Bad.pdf|Plots]]
 
** [[:media:1663-Plots-ADC-33-Bad.pdf|Plots]]
 
** All but channel 6 are bad
 
** All but channel 6 are bad
 
** No error code - just bad channel responses
 
** No error code - just bad channel responses
−
* Run 1664 - ADC 31 - bad
+
* Run 1664 - test '''ADC 31'''
 
** [[:media:1664-Plots-ADC-33-Bad.pdf|Plots]]
 
** [[:media:1664-Plots-ADC-33-Bad.pdf|Plots]]
−
** There are read errors for 1/3 events or so
+
** There are ROC read errors for 1/3 events or so
 
** All channels have crazy noise and no response to input voltage
 
** All channels have crazy noise and no response to input voltage
 
** Read errors get worse when plugging a signal into a channel
 
** Read errors get worse when plugging a signal into a channel
 
** Some channels show differing response to input... characterizing problems will be a bit hard, so assume normal input stage problems? Or wiring to the later stages is bad across all channels?
 
** Some channels show differing response to input... characterizing problems will be a bit hard, so assume normal input stage problems? Or wiring to the later stages is bad across all channels?
−
* Run 1665 - ADC 31 - bad
+
* Run 1665 - test '''ADC 31'''
 
** [[:media:1665-Plots-ADC-31-Bad.pdf|Plots]]
 
** [[:media:1665-Plots-ADC-31-Bad.pdf|Plots]]
 
** Same ADC, same issues, rebooting VME crate didn't help
 
** Same ADC, same issues, rebooting VME crate didn't help
 
** All 8 channels are bad, but some appear to have effects on their neighbors?
 
** All 8 channels are bad, but some appear to have effects on their neighbors?
−
* Run 1666 - ADC 3 - a repaired board, previously tested in run 4642 in CH crate in November
+
* Run 1666 - test '''ADC 3''' - a repaired board, previously tested in run 4642 in CH crate in November
 
** [[:media:4542-Plots-ADC-3-OLD-Bad.pdf|Plots - old bad]]
 
** [[:media:4542-Plots-ADC-3-OLD-Bad.pdf|Plots - old bad]]
 
** [[:media:1666-Plots-ADC-3-NEW-Good-abridged.pdf|Plots - new fixed, abridged plots (zoom x axis for ease of viewing)]]
 
** [[:media:1666-Plots-ADC-3-NEW-Good-abridged.pdf|Plots - new fixed, abridged plots (zoom x axis for ease of viewing)]]
Line 53: Line 53:
 
** So Mark Taylor has fixed the board.
 
** So Mark Taylor has fixed the board.
 
** Here are plots comparing channel (indexed) 1, 2, and 3 [[:media:4542-Plots-ADC-3-OLD-Bad-only.pdf|old data]] with [[:media:1666-Plots-ADC-3-NEW-Good-only.pdf|new]]
 
** Here are plots comparing channel (indexed) 1, 2, and 3 [[:media:4542-Plots-ADC-3-OLD-Bad-only.pdf|old data]] with [[:media:1666-Plots-ADC-3-NEW-Good-only.pdf|new]]
−
* Run 1667 - ADC 6
+
* Run 1667 - test '''ADC 6'''
 
** [[:media:1668-Plots-ADC-6-Good.pdf|Plots]]
 
** [[:media:1668-Plots-ADC-6-Good.pdf|Plots]]
 
** All channels look good
 
** All channels look good

Revision as of 17:30, 15 February 2019

Back to Main Page >> DAQ Documentation Portal >> DAQ Testing

We will log bad boards and upload plots and descriptions of problems to: https://misportal.jlab.org/mis/apps/peer/submit.cfm

  • Run 1654 - testing a board to replace CH "vqwk1" "bad" board
    • Plots
    • It works, this board can be used - has label on top "MDBKG"
    • This board is then used to replace the board in CH "vqwk1" and Tao has taken data to establish pedestals
    • HAPLOG 3619 describes BPM 8 test with new ADC in CH crate
    • run 1233 and 1234 were used to test (run 1233 had address conflict, so ignore)
  • Run 1655 - test ADC 26
  • Run 1656 - testing original CH "vqwk1" "bad" board (top 4 channels are bad, ch's 4-7).
    • Plots
    • Top 4 channels are bad, as seen in CH crate data
  • Run 1657 - test ADC 15, the one with the strangely wired and tied on Op Amp
  • Run 1658 - test ADC 37 - ISU board that has recently had new channels go bad on it
    • Plots
    • Bad channels 2, 3, 4
    • Channels 2 and 4 are highly non-linear, basically flat lines offset from pedestal
    • Channel 3 works only in positive voltage range
    • No Japan error codes are reported
  • Run 1659 - test ADC 32 - used wrong HW address, no ACC light blinking and many VQWK read errors on telnet session
  • Run 1660-1662 - test ADC 32 - corrected HW address (needs to be 0x8400)
  • Run 1663 - test ADC 33 - ISU backup board
    • Plots
    • All but channel 6 are bad
    • No error code - just bad channel responses
  • Run 1664 - test ADC 31
    • Plots
    • There are ROC read errors for 1/3 events or so
    • All channels have crazy noise and no response to input voltage
    • Read errors get worse when plugging a signal into a channel
    • Some channels show differing response to input... characterizing problems will be a bit hard, so assume normal input stage problems? Or wiring to the later stages is bad across all channels?
  • Run 1665 - test ADC 31
    • Plots
    • Same ADC, same issues, rebooting VME crate didn't help
    • All 8 channels are bad, but some appear to have effects on their neighbors?
  • Run 1666 - test ADC 3 - a repaired board, previously tested in run 4642 in CH crate in November
  • Run 1667 - test ADC 6
    • Plots
    • All channels look good

Status

Most spare boards have problems, but Mark Taylor can fix them

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