Difference between revisions of "TEDf-VQWK-Testing"

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*** I started a new run to clear read error messages, that didn't fix, so I rebooted, and after rebooting the data is clear - no signal/analog output from ADC channels
 
*** I started a new run to clear read error messages, that didn't fix, so I rebooted, and after rebooting the data is clear - no signal/analog output from ADC channels
 
** I removed the board and marked it as dead
 
** I removed the board and marked it as dead
 +
** '''Mark Taylor has since fixed it'''
 +
*** Run 1742 - [[:media:1742-Plots-ADC-32-NEW-Good.pdf| Plots]]
 
* Run 1663 - test '''ADC 33''' - ISU backup board
 
* Run 1663 - test '''ADC 33''' - ISU backup board
 
** [[:media:1663-Plots-ADC-33-Bad.pdf|Plots]]
 
** [[:media:1663-Plots-ADC-33-Bad.pdf|Plots]]
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** So Mark Taylor has fixed the board.
 
** So Mark Taylor has fixed the board.
 
** Here are plots comparing channel (indexed) 1, 2, and 3 [[:media:4542-Plots-ADC-3-OLD-Bad-only.pdf|old data]] with [[:media:1666-Plots-ADC-3-NEW-Good-only.pdf|new]]
 
** Here are plots comparing channel (indexed) 1, 2, and 3 [[:media:4542-Plots-ADC-3-OLD-Bad-only.pdf|old data]] with [[:media:1666-Plots-ADC-3-NEW-Good-only.pdf|new]]
 +
** I tested it again, for good measure: [[:media:1741-Plots-ADC-3-NEW-Good.pdf|Here]]
 
* Run 1668 - test '''ADC 6'''
 
* Run 1668 - test '''ADC 6'''
 
** [[:media:1668-Plots-ADC-6-Good.pdf|Plots]]
 
** [[:media:1668-Plots-ADC-6-Good.pdf|Plots]]
Line 102: Line 105:
 
** '''Mark Taylor has now fixed it''' - 3/14/2019
 
** '''Mark Taylor has now fixed it''' - 3/14/2019
 
* ADC 32
 
* ADC 32
** '''Determined not to work''' - 2/14/2019
+
** Determined not to work - 2/14/2019
 
** All 8 channels have interesting problems
 
** All 8 channels have interesting problems
 
** It looks like regular bad amplifier in input stage problems
 
** It looks like regular bad amplifier in input stage problems
 
** But, in the third run I took with this board it looks like the signal stopped being read by digital components entirely (run 1662, all signals == 0)
 
** But, in the third run I took with this board it looks like the signal stopped being read by digital components entirely (run 1662, all signals == 0)
 +
** '''Mark Taylor has now fixed it''' - 3/19/2019
 
* ADC 33
 
* ADC 33
 
** Determined not to work - 2/15/2019
 
** Determined not to work - 2/15/2019

Revision as of 12:21, 19 March 2019

Back to Main Page >> DAQ Documentation Portal >> DAQ Testing

Board Testing

We will log bad boards and upload plots and descriptions of problems to: https://misportal.jlab.org/mis/apps/peer/submit.cfm

  • Run 1654 - testing a board to replace CH "vqwk1" "bad" board
    • Plots
    • It works, this board can be used - has label on top "MDBKG"
    • This board is then used to replace the board in CH "vqwk1" and Tao has taken data to establish pedestals
    • HAPLOG 3619 describes BPM 8 test with new ADC in CH crate
    • run 1233 and 1234 were used to test (run 1233 had address conflict, so ignore)
  • Run 1655 - test ADC 26
  • Run 1656 - test ADC 20 - testing original CH "vqwk1" "bad" board (top 4 channels are bad, ch's 4-7).
    • Plots
    • Top 4 channels are bad, as seen in CH crate data
  • Run 1657 - test ADC 15, the one with the strangely wired and tied on Op Amp
  • Run 1658 - test ADC 37 - ISU board that has recently had new channels go bad on it
    • Plots
    • Bad channels 2, 3, 4
    • Channels 2 and 4 are highly non-linear, basically flat lines offset from pedestal
    • Channel 3 works only in positive voltage range
    • No Japan error codes are reported
  • Run 1659 - test ADC 32 - used wrong HW address, no ACC light blinking and many VQWK read errors on telnet session
  • Run 1660-1662 - test ADC 32 - corrected HW address (needs to be 0x8400)
  • Run 1663 - test ADC 33 - ISU backup board
    • Plots
    • All but channel 6 are bad
    • No error code - just bad channel responses
  • Run 1664 - test ADC 31
    • Plots
    • There are ROC read errors for 1/3 events or so
    • All channels have crazy noise and no response to input voltage
    • Read errors get worse when plugging a signal into a channel
    • Some channels show differing response to input... characterizing problems will be a bit hard, so assume normal input stage problems? Or wiring to the later stages is bad across all channels?
  • Run 1665 - test ADC 31
    • Plots
    • Same ADC, same issues, rebooting VME crate didn't help
    • All 8 channels are bad, but some appear to have effects on their neighbors?
  • Run 1666 - test ADC 3 - a repaired board, previously tested in run 4642 in CH crate in November
  • Run 1668 - test ADC 6
    • Plots
    • All channels look good
  • Run 1690 - test ADC 20
    • Plots
    • All channels look good - fixed by Mark Taylor
  • Run 1691 - test ADC 37
    • Plots
    • All channels look good - fixed by Mark Taylor
  • Run 1710 - test ADC 8
    • Plots
    • All channels look good - fixed by Mark Taylor
  • Run 1713 - test ADC 33
    • Plots
    • All channels look good - fixed by Mark Taylor
  • Run 1714 - test ADC 31
    • Plots
    • All channels look good - fixed by Mark Taylor

Status

Most spare boards have problems, but Mark Taylor can fix them

9 out of 72 spare channels are bad.

Catalog

  • ADC 3
    • Fixed by Mark Taylor - 2/15/2019
  • ADC 6
    • Determined to work - 2/15/2019
  • ADC 8
    • No pre-fix test given
    • Mark Taylor has now fixed it - 3/14/2019
  • ADC 15
    • Determined to work - 2/13/2019
  • ADC 20
    • Determined not to work - 2/13/2019
    • Channels 4-7 (top 4) do not work
    • Signal ramps to -10 V for all events, regardless of containing a voltage signal or not
    • Mark Taylor has now fixed it - 3/1/2019
  • ADC 26
    • Determined to work - 2/14/2019
  • ADC 31
    • Determined not to work - 2/15/2019
    • There are ROC read errors for 1/3 events or so
    • All channels have randomly stepping noisy signal that rails into certain regions and no clear response to input voltage
    • ROC Read errors get worse when plugging a signal into a channel
    • Some channels show differing response to input... characterizing problems will be a bit hard, so assume normal input stage problems? Or wiring to the later stages is bad across all channels?
    • Mark Taylor has now fixed it - 3/14/2019
  • ADC 32
    • Determined not to work - 2/14/2019
    • All 8 channels have interesting problems
    • It looks like regular bad amplifier in input stage problems
    • But, in the third run I took with this board it looks like the signal stopped being read by digital components entirely (run 1662, all signals == 0)
    • Mark Taylor has now fixed it - 3/19/2019
  • ADC 33
    • Determined not to work - 2/15/2019
    • Regular bad channels
    • Channel 6 "works" but probably it would be best to go ahead and give it a standard replacement treatment too?
    • Mark Taylor has now fixed it - 3/14/2019
  • ADC 37
    • Determined not to work - 2/14/2019
    • A few channels are bad - 2, 3, 4 (index, starts at 0 in software, starts at 1 on board face)
    • Mark Taylor has now fixed it - 3/1/2019
    • Pre-fix full plots of toggle-pair-asymmetry: Plots
    • Post-fix full plots of toggle-pair-asymmetry: Plots