TEDf-VQWK-Testing

From PREX Wiki
Jump to: navigation, search

Back to Main Page >> DAQ Documentation Portal >> DAQ Testing

ADC Wait Delay Effect

It is likely that the ADC internal wait delay needs to be > 0 so that the ADC will integrate it's number of samples uniformly. In order to test this hypothesis we should stick a stable signal into an ADC channel and scan both wait delay time and the number of samples per block in order to determine when/for how long the first block is modified w.r.t. other blocks as a function of wait delay time.

The TEDf test stand runs 1783- are testing this hypothesis.

  • Run 1783 - initial baseline adc wait time effect test (4141 nsamp per block), wait time to 0
  • Run 1784 - 1/4 samples - 1035 samp per block - too short
  • Run 1785 - 1/4 samples - 1035 samp per block - WriteHelBoard(1,27)
  • Run 1786 - 1/4 samples - 260 samp per block - WriteHelBoard(1,14)
  • Run 1787 - 1/4 samples - 120 samp per block - WriteHelBoard(1,9)
  • Run 1788 - 1/4 samples - 120 samp per block - WriteHelBoard(1,9)
  • Run 1789 - 1/4 samples - 120 samp per block - WriteHelBoard(1,9)
  • Run 1790 - small samp - 120 samp per block - vqwk wait back to 10
  • Run 1791 - small samp - 120 samp per block - vqwk wait to 20

Board Testing

We will log bad boards and upload plots and descriptions of problems to: https://misportal.jlab.org/mis/apps/peer/submit.cfm

  • Run 1654 - testing a board to replace CH "vqwk1" "bad" board
    • Plots
    • It works, this board can be used - has label on top "MDBKG"
    • This board is then used to replace the board in CH "vqwk1" and Tao has taken data to establish pedestals
    • HAPLOG 3619 describes BPM 8 test with new ADC in CH crate
    • run 1233 and 1234 were used to test (run 1233 had address conflict, so ignore)
  • Run 1655 - test ADC 26
  • Run 1656 - test ADC 20 - testing original CH "vqwk1" "bad" board (top 4 channels are bad, ch's 4-7).
    • Plots
    • Top 4 channels are bad, as seen in CH crate data
  • Run 1657 - test ADC 15, the one with the strangely wired and tied on Op Amp
  • Run 1658 - test ADC 37 - ISU board that has recently had new channels go bad on it
    • Plots
    • Bad channels 2, 3, 4
    • Channels 2 and 4 are highly non-linear, basically flat lines offset from pedestal
    • Channel 3 works only in positive voltage range
    • No Japan error codes are reported
  • Run 1659 - test ADC 32 - used wrong HW address, no ACC light blinking and many VQWK read errors on telnet session
  • Run 1660-1662 - test ADC 32 - corrected HW address (needs to be 0x8400)
  • Run 1663 - test ADC 33 - ISU backup board
    • Plots
    • All but channel 6 are bad
    • No error code - just bad channel responses
  • Run 1664 - test ADC 31
    • Plots
    • There are ROC read errors for 1/3 events or so
    • All channels have crazy noise and no response to input voltage
    • Read errors get worse when plugging a signal into a channel
    • Some channels show differing response to input... characterizing problems will be a bit hard, so assume normal input stage problems? Or wiring to the later stages is bad across all channels?
  • Run 1665 - test ADC 31
    • Plots
    • Same ADC, same issues, rebooting VME crate didn't help
    • All 8 channels are bad, but some appear to have effects on their neighbors?
  • Run 1666 - test ADC 3 - a repaired board, previously tested in run 4642 in CH crate in November
  • Run 1668 - test ADC 6
    • Plots
    • All channels look good
  • Run 1690 - test ADC 20
    • Plots
    • All channels look good - fixed by Mark Taylor
  • Run 1691 - test ADC 37
    • Plots
    • All channels look good - fixed by Mark Taylor
  • Run 1710 - test ADC 8
    • Plots
    • All channels look good - fixed by Mark Taylor
  • Run 1713 - test ADC 33
    • Plots
    • All channels look good - fixed by Mark Taylor
  • Run 1714 - test ADC 31
    • Plots
    • All channels look good - fixed by Mark Taylor

ADC 1

ADC 1 was previously in the hall and had a bad channel (labelled bad, and was bad).

Status

Most spare boards have problems, but Mark Taylor can fix them

1 out of 56 spare channels are bad.

Catalog

  • ADC 1
    • Known not to work - 3/28/2019
    • Fixed by Mark Taylor - 5/23/2019
    • New problem found in channel 5 - non-linearity - 6/4/2019
  • ADC 3
    • Fixed by Mark Taylor - 2/15/2019
  • ADC 6
    • Determined to work - 2/15/2019
  • ADC 8
    • No pre-fix test given
    • Mark Taylor has now fixed it - 3/14/2019
  • ADC 15
    • Determined to work - 2/13/2019
  • ADC 20
    • Determined not to work - 2/13/2019
    • Channels 4-7 (top 4) do not work
    • Signal ramps to -10 V for all events, regardless of containing a voltage signal or not
    • Mark Taylor has now fixed it - 3/1/2019
  • ADC 26
    • Determined to work - 2/14/2019
  • ADC 31
    • Determined not to work - 2/15/2019
    • There are ROC read errors for 1/3 events or so
    • All channels have randomly stepping noisy signal that rails into certain regions and no clear response to input voltage
    • ROC Read errors get worse when plugging a signal into a channel
    • Some channels show differing response to input... characterizing problems will be a bit hard, so assume normal input stage problems? Or wiring to the later stages is bad across all channels?
    • Mark Taylor has now fixed it - 3/14/2019
  • ADC 32
    • Determined not to work - 2/14/2019
    • All 8 channels have interesting problems
    • It looks like regular bad amplifier in input stage problems
    • But, in the third run I took with this board it looks like the signal stopped being read by digital components entirely (run 1662, all signals == 0)
    • Mark Taylor has now fixed it - 3/19/2019
  • ADC 33
    • Determined not to work - 2/15/2019
    • Regular bad channels
    • Channel 6 "works" but probably it would be best to go ahead and give it a standard replacement treatment too?
    • Mark Taylor has now fixed it - 3/14/2019
  • ADC 37
    • Determined not to work - 2/14/2019
    • A few channels are bad - 2, 3, 4 (index, starts at 0 in software, starts at 1 on board face)
    • Mark Taylor has now fixed it - 3/1/2019
    • Pre-fix full plots of toggle-pair-asymmetry: Plots
    • Post-fix full plots of toggle-pair-asymmetry: Plots